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ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 1 ? 2009?2011 xilinx, inc. xilinx, the xilinx logo, virtex, spartan, ise, and other designated brands included herein are tradema rks of xilinx in the united states and other countries. all other trademarks are the property of their respective owners. virtex-6 fpga electrical characteristics virtex?-6 fpgas are available in -3, -2, -1, and -1l speed grades, with -3 having the highest performance. virtex-6 fpga dc and ac characteristics are specified for both commercial and industrial grades. except the operating temperature range or unless otherwise noted, all the dc and ac electrical parameters are the same for a particular speed grade (that is, the timing characteristics of a -1 speed grade industrial device are the same as for a -1 speed grade commercial device). however, only selected speed grades and/or devices might be available in the industrial range. all supply voltage and junction temperature specifications are representative of worst-case conditions. the parameters included are common to popular designs and typical applications. this virtex-6 fpga data sheet, part of an overall set of documentation on the virtex-6 family of fpgas, is available on the xilinx website. all specifications are subject to change without notice. virtex-6 fpga dc characteristics virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 advance product specification ta bl e 1 : absolute maximum ratings (1) symbol description units v ccint internal supply voltage re lative to gnd ?0.5 to 1.1 v for -1l devices: internal supply voltage relative to gnd ?0.5 to 1.0 v v ccaux auxiliary supply voltage relative to gnd ?0.5 to 3.0 v v cco output drivers supply voltage relative to gnd ?0.5 to 3.0 v v batt key memory battery backup supply ?0.5 to 3.0 v v fs external voltage supply for efuse programming (2) ?0.5 to 3.0 v v ref input reference voltage ?0.5 to 3.0 v v in (3) 2.5v or below i/o input voltage relative to gnd (4) (user and dedicated i/os) ?0.5 to v cco +0.5 v v ts voltage applied to 3-state 2.5v or below output (4) (user and dedicated i/os) ?0.5 to v cco +0.5 v t stg storage temperature (ambient) ?65 to 150 c t sol maximum soldering temperature (5) +220 c t j maximum junction temperature (5) +125 c notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not i mplied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. 2. when not programming efuse, connect v fs to gnd. 3. 2.5v i/o absolute maximum limit applied to dc and ac signals. 4. for i/o operation, refer to the virtex-6 fpga selectio resources user guide . 5. for soldering guidelines and thermal considerations, see virtex-6 fpga packaging and pinout specification .
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 2 ta bl e 2 : recommended operating conditions symbol description min max units v ccint internal supply voltage relative to gnd, t j = 0c to +85c 0.95 1.05 v internal supply voltage relative to gnd, t j = ?40c to +100c 0.95 1.05 v for -2 industrial temperature range, xc 6vsx475t, xc6vlx550t , xc6vlx760, and xc6vhx565tdevices: internal supply voltage relative to gnd, t j = 0c to +100c 0.95 1.05 v for -1l commercial temperature range devi ces: internal supply voltage relative to gnd, t j = 0c to +85c 0.87 0.93 v for -1l industrial temperature range devices: internal supply voltage relative to gnd, t j = ?40c to +100c 0.91 0.97 v v ccaux auxiliary supply voltage relative to gnd, t j = 0c to +85c 2.375 2.625 v auxiliary supply voltage relative to gnd, t j = ?40c to +100c 2.375 2.625 v for -2 industrial temperature range, xc 6vsx475t, xc6vlx550t , xc6vlx760, and xc6vhx565tdevices: auxiliary supply voltage relative to gnd, t j = 0c to +100c 2.375 2.625 v v cco (1)(3)(4) supply voltage relative to gnd, t j = 0c to +85c 1.14 2.625 v supply voltage relative to gnd, t j = ?40c to +100c 1.14 2.625 v for -2 industrial temperature range, xc 6vsx475t, xc6vlx550t , xc6vlx760, and xc6vhx565tdevices: supply voltage relative to gnd, t j = 0c to +100c 1.14 2.625 v v in 2.5v supply voltage relative to gnd, t j = 0c to +85c gnd ? 0.20 2.625 v 2.5v supply voltage relative to gnd, t j = ?40c to +100c gnd ? 0.20 2.625 v for -2 industrial temperature range, xc 6vsx475t, xc6vlx550t , xc6vlx760, and xc6vhx565tdevices: 2.5v supply voltage relative to gnd, t j = 0c to +100c gnd ? 0.20 2.625 v 2.5v and below supply voltage relative to gnd, t j = 0c to +85c gnd ? 0.20 v cco +0.2 v 2.5v and below supply voltage relative to gnd, t j = ?40c to +100c gnd ? 0.20 v cco +0.2 v for -2 industrial temperature range, xc 6vsx475t, xc6vlx550t , xc6vlx760, and xc6vhx565tdevices: 2.5v and below supply voltage relative to gnd, t j = 0c to +100c gnd ? 0.20 v cco +0.2 v i in (6) maximum current through any pin in a powered or unpowered bank when forward biasing the clamp diode. ?10ma v batt (2) battery voltage relative to gnd, t j = 0c to +85c 1.0 2.5 v battery voltage relative to gnd, t j = ?40c to +100c 1.0 2.5 v for -2 industrial temperature range, xc 6vsx475t, xc6vlx550t , xc6vlx760, and xc6vhx565tdevices: battery voltage relative to gnd, t j = 0c to +100c 1.0 2.5 v v fs (7) external voltage supply for efuse programming 2.375 2.625 v notes: 1. configuration data is retained even if v cco drops to 0v. 2. v batt is required only when using bitstream encryption. if battery is not used, connect v batt to either ground or v ccaux . 3. includes v cco of 1.2v, 1.5v, 1.8v, and 2.5v. 4. the configuration supply voltage v cc_config is also known as v cco_0 . 5. all voltages are relative to ground. 6. a total of 100 ma per bank should not be exceeded. 7. when not programming efuse, connect v fs to gnd.
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 3 ta bl e 3 : dc characteristics over recommended operating conditions (1)(2) symbol description min typ max units v drint data retention v ccint voltage (below which configuration data might be lost) 0.75 ? ? v v dri data retention v ccaux voltage (below which configuration data might be lost) 2.0 ? ? v i ref v ref leakage current per pin ? ? 10 a i l input or output leakage current per pin (sample-tested) ? ? 10 a c in (3) die input capacitance at the pad ? ? 8 pf i rpu pad pull-up (when selected) @ v in =0v, v cco =2.5v 20?80a pad pull-up (when selected) @ v in =0v, v cco =1.8v 8 ? 40 a pad pull-up (when selected) @ v in =0v, v cco =1.5v 5 ? 30 a pad pull-up (when selected) @ v in =0v, v cco =1.2v 1 ? 20 a i rpd pad pull-down (when selected) @ v in =2.5v 3 ? 80 a i batt battery supply current ? ? 150 na n temperature diode ideality factor ? 1.0002 ? n r series resistance ? 5 ? ? notes: 1. typical values are specified at nominal voltage, 25c. 2. maximum value specified for worst case process at 25c. 3. this measurement represents the die capacitance at the pad, not including the package.
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 4 important note typical values for quiescent supply current are specified at nominal voltage, 85c junction temperatures (t j ). xilinx recommends analyzing static power consumption at t j = 85c because the majority of designs operate near the high end of the commercial temperature range. quiescent supply current is specified by speed grade for virtex-6 devices. use the xpower? estimator (xpe) spreadsheet tool (download at http://www.xilinx.com/power ) to calculate static power consumption for conditions other than those specified in ta bl e 4 . ta bl e 4 : typical quiescent supply current symbol description device speed and temperature grade units -3 (c) -2 (c & i) (1) -1 (c & i) -1l (c) -1l (i) (2) i ccintq quiescent v ccint supply current xc6vlx75t 927 927 927 656 741 ma xc6vlx130t 1563 1563 1563 1102 1245 ma xc6vlx195t 2059 2059 2059 1441 1628 ma xc6vlx240t 2478 2478 2478 1733 1957 ma xc6vlx365t 3001 3001 3001 2092 2363 ma xc6vlx550t n/a 4515 4515 3147 3555 ma xc6vlx760 n/a 5094 5094 3471 3921 ma xc6vsx315t 3476 3476 3476 2409 2721 ma xc6vsx475t n/a 5227 5227 3622 4091 ma xc6vhx250t 2906 2906 2906 n/a n/a ma xc6vhx255t n/a n/a ma xc6vhx380t n/a n/a ma xc6vhx565t n/a n/a n/a ma i ccoq quiescent v cco supply current xc6vlx75t11111ma xc6vlx130t11111ma xc6vlx195t11111ma xc6vlx240t22222ma xc6vlx365t22222ma xc6vlx550tn/a3333ma xc6vlx760n/a3333ma xc6vsx315t 22222ma xc6vsx475t n/a 2222ma xc6vhx250t 1 1 1 n/a n/a ma xc6vhx255t n/a n/a ma xc6vhx380t n/a n/a ma xc6vhx565t n/a n/a n/a ma
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 5 i ccauxq quiescent v ccaux supply current xc6vlx75t4545454545ma xc6vlx130t 75 75 75 75 75 ma xc6vlx195t 113 113 113 113 113 ma xc6vlx240t 135 135 135 135 135 ma xc6vlx365t 191 191 191 191 191 ma xc6vlx550t n/a 286 286 286 286 ma xc6vlx760 n/a 387 387 387 387 ma xc6vsx315t 186 186 186 186 186 ma xc6vsx475t n/a 279 279 279 279 ma xc6vhx250t 152 152 152 n/a n/a ma xc6vhx255t n/a n/a ma xc6vhx380t n/a n/a ma xc6vhx565t n/a n/a n/a ma notes: 1. the xc6vlx550t, xc6vlx760, xc6vsx475t, and xc6vhx565t are not offered in -2i. 2. typical values are specified at nominal voltage, 85c junction temperatures (t j ). -1, -2, and -3 industrial (i) grade devices have the same typical values as commercial (c) grade devices at 85c, but higher values at 100c. use the xpe tool to calculate 100c values. -1l industrial grade devices have the values specified in this column. 3. typical values are for blank configured devices with no output current loads, no active input pull-up resistors, all i/o pins are 3-state and floating. 4. if dci or differential signaling is used, more accurate quiescent current estimates can be obtained by using the xpower estim ator (xpe) or xpower analyzer (xpa) tools. ta bl e 4 : typical quiescent supply current (cont?d) symbol description device speed and temperature grade units -3 (c) -2 (c & i) (1) -1 (c & i) -1l (c) -1l (i) (2)
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 6 power-on power supply requirements xilinx fpgas require a certain amount of su pply current during power-on to insure proper device initialization. the actual current consumed depends on the power-on ramp rate of the power supply. virtex-6 devices require a power-on sequence of v ccint , v ccaux , and v cco . if the requirement can not be met, then v ccaux must always be powered prior to v cco . v ccaux and v cco can be powered by the same supply, therefore, both v ccaux and v cco are permitted to ramp simultaneously. similarly, for the power-down sequence, v cco must be powered down prior to v ccaux or if power by the same supply, v ccaux and v cco power-down simultaneously. ta bl e 5 shows the minimum current, in addition to i ccq , that are required by virtex-6 devices for proper power-on and configuration. if the current minimums shown in ta bl e 4 and ta bl e 5 are met, the device powers on after all three supplies have passed through their power-on reset threshold voltages. the fpga must be configured after v ccint is applied. once initialized and configured, use the xpower tools to estimate current drain on these supplies. ta bl e 5 : power-on current for virtex-6 devices device i ccintmin i ccauxmin i ccomin units typ (1) typ (1) typ (1) xc6vlx75t see i ccintq in ta bl e 4 i ccauxq +10 i ccoq + 30 ma per bank ma xc6vlx130t see i ccintq in ta bl e 4 i ccauxq +10 i ccoq + 30 ma per bank ma xc6vlx195t see i ccintq in ta bl e 4 i ccauxq +40 i ccoq + 30 ma per bank ma xc6vlx240t see i ccintq in ta bl e 4 i ccauxq +40 i ccoq + 30 ma per bank ma xc6vlx365t see i ccintq in ta bl e 4 i ccauxq +40 i ccoq + 30 ma per bank ma xc6vlx550t see i ccintq in ta bl e 4 i ccauxq +40 i ccoq + 30 ma per bank ma xc6vlx760 see i ccintq in ta bl e 4 i ccauxq +40 i ccoq + 30 ma per bank ma xc6vsx315t see i ccintq in ta bl e 4 i ccauxq +40 i ccoq + 30 ma per bank ma xc6vsx475t see i ccintq in ta bl e 4 i ccauxq +50 i ccoq + 30 ma per bank ma xc6vhx250t see i ccintq in ta bl e 4 i ccauxq +40 i ccoq + 30 ma per bank ma xc6vhx255t ma xc6vhx380t ma xc6vhx565t ma notes: 1. typical values are specified at nominal voltage, 25c. 2. use the xpower? estimator (xpe) spreadsheet tool (download at http://www.xilinx.com/power ) to calculate maximum power-on currents. ta bl e 6 : power supply ramp time symbol description ramp time units v ccint internal supply voltage relative to gnd 0.20 to 50.0 ms v cco output drivers supply voltage relative to gnd 0.20 to 50.0 ms v ccaux auxiliary supply voltage relative to gnd 0.20 to 50.0 ms
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 7 selectio? dc input and output levels values for v il and v ih are recommended input voltages. values for i ol and i oh are guaranteed over the recommended operating conditions at the v ol and v oh test points. only selected standards are tested. these are chosen to ensure that all standards meet their specifications. the selected standards are tested at a minimum v cco with the respective v ol and v oh voltage levels shown. other standards are sample tested. ta bl e 7 : selectio dc input and output levels i/o standard v il v ih v ol v oh i ol i oh v, min v, max v, min v, max v, max v, min ma ma lvcmos25, lvdci25 ?0.3 0.7 1.7 v cco +0.3 0.4 v cco ? 0.4 note(3) note(3) lvcmos18, lvdci18 ?0.3 35% v cco 65% v cco v cco + 0.3 0.45 v cco ? 0.45 note(4) note(4) lvcmos15, lvdci15 ?0.3 35% v cco 65% v cco v cco + 0.3 25% v cco 75% v cco note(4) note(4) lvcmos12 ?0.3 35% v cco 65% v cco v cco + 0.3 25% v cco 75% v cco note(5) note(5) hstl i_12 ?0.3 v ref ?0.1 v ref +0.1 v cco + 0.3 25% v cco 75% v cco 6.3 6.3 hstl i (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ?0.4 8 ?8 hstl ii (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ?0.4 16 ?16 hstl iii (2) ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 0.4 v cco ? 0.4 24 ?8 diff hstl i (2) ?0.3 50% v cco ? 0.1 50% v cco +0.1 v cco +0.3 ? ? ? ? diff hstl ii (2) ?0.3 50% v cco ? 0.1 50% v cco +0.1 v cco +0.3 ? ? ? ? sstl2 i ?0.3 v ref ?0.15 v ref +0.15 v cco +0.3 v tt ?0.61 v tt + 0.61 8.1 ?8.1 sstl2 ii ?0.3 v ref ?0.15 v ref +0.15 v cco +0.3 v tt ?0.81 v tt + 0.81 16.2 ?16.2 diff sstl2 i ?0.3 50% v cco ?0.15 50% v cco +0.15 v cco +0.3 ? ? ? ? diff sstl2 ii ?0.3 50% v cco ?0.15 50% v cco +0.15 v cco +0.3 ? ? ? ? sstl18 i ?0.3 v ref ? 0.125 v ref + 0.125 v cco +0.3 v tt ?0.47 v tt + 0.47 6.7 ?6.7 sstl18 ii ?0.3 v ref ? 0.125 v ref +0.125 v cco +0.3 v tt ?0.60 v tt + 0.60 13.4 ?13.4 diff sstl18 i ?0.3 50% v cco ?0.125 50% v cco +0.125 v cco +0.3 ? ? ? ? diff sstl18 ii ?0.3 50% v cco ?0.125 50% v cco +0.125 v cco +0.3 ? ? ? ? sstl15 ?0.3 v ref ?0.1 v ref +0.1 v cco +0.3 v tt ?0.175 v tt + 0.175 14.3 14.3 notes: 1. tested according to relevant specifications. 2. applies to both 1.5v and 1.8v hstl. 3. using drive strengths of 2, 4, 6, 8, 12, 16, or 24 ma. 4. using drive strengths of 2, 4, 6, 8, 12, or 16 ma. 5. supported drive strengths of 2, 4, 6, or 8 ma. 6. for detailed interface specific dc voltage levels, see the virtex-6 fpga selectio resources user guide .
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 8 ht dc specifications (ht_25) lvds dc specifications (lvds_25) extended lvds dc specif ications (lvdsext_25) ta bl e 8 : ht dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 2.38 2.5 2.63 v v od differential output voltage r t = 100 ? across q and q signals 480 600 885 mv ? v od change in v od magnitude ?15 ? 15 mv v ocm output common mode voltage r t = 100 ? across q and q signals 440 600 760 mv ? v ocm change in v ocm magnitude ?15 ? 15 mv v id input differential voltage 200 600 1000 mv ? v id change in v id magnitude ?15 ? 15 mv v icm input common mode voltage 440 600 780 mv ? v icm change in v icm magnitude ?15 ? 15 mv ta bl e 9 : lvds dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 2.38 2.5 2.63 v v oh output high voltage for q and q r t = 100 ? across q and q signals ? ? 1.675 v v ol output low voltage for q and q r t = 100 ? across q and q signals 0.825 ? ? v v odiff differential output voltage (q ? q ), q = high (q ?q), q =high r t = 100 ? across q and q signals 247 350 600 mv v ocm output common-mode voltage r t = 100 ? across q and q signals 1.075 1.250 1.425 v v idiff differential input voltage (q ? q ), q = high (q ?q), q =high 100 350 600 mv v icm input common-mode voltage 0.3 1.2 2.2 v ta bl e 1 0 : extended lvds dc specifications symbol dc parameter conditions min typ max units v cco supply voltage 2.38 2.5 2.63 v v oh output high voltage for q and q r t = 100 ? across q and q signals ? ? 1.785 v v ol output low voltage for q and q r t = 100 ? across q and q signals 0.715 ? ? v v odiff differential output voltage (q ? q ), q = high (q ?q), q =high r t = 100 ? across q and q signals 350 ? 840 mv v ocm output common-mode voltage r t = 100 ? across q and q signals 1.075 1.250 1.425 v v idiff differential input voltage (q ? q ), q = high (q ?q), q =high common-mode input voltage = 1.25v 100 ? 1000 mv v icm input common-mode voltage differentia l input voltage = 350 mv 0.3 1.2 2.2 v
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 9 lvpecl dc specifi cations (lvpecl_25) these values are valid when driving a 100 ? differential load only, i.e., a 100 ? resistor between the two receiver pins. the v oh levels are 200 mv below standard lvpecl levels and are co mpatible with devices toler ant of lower common-mode ranges. ta bl e 1 1 summarizes the dc output specif ications of lvpecl. for more information on using lvpecl , see the virtex-6 fpga selectio resources user guide . efuse read endurance ta bl e 1 2 lists the maximum number of read cycle operations expected. for more information, see the virtex-6 fpga configuration user guide . ta bl e 1 1 : lvpecl dc specifications symbol dc parameter min typ max units v oh output high voltage v cc ? 1.025 1.545 v cc ?0.88 v v ol output low voltage v cc ? 1.81 0.795 v cc ?1.62 v v icm input common-mode voltage 0.6 ? 2.2 v v idiff differential input voltage (1)(2) 0.100 ? 1.5 v notes: 1. recommended input maximum voltage not to exceed v ccaux +0.2v. 2. recommended input minimum voltage not to go below ?0.5v. ta bl e 1 2 : efuse read endurance symbol description speed grade units -3 -2 -1 -1l dna_cycles number of dna_port read operations or jtag isc_dna read command operations. unaffected by shift operations. 30,000,000 read cycles aes_cycles number of jtag fuse_key or fuse_cntl read command operations. unaffected by shift operations. 30,000,000 read cycles
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 10 gtx transceiver specifications gtx transceiver dc characteristics ta bl e 1 3 : absolute maximum ratings for gtx transceivers (1) symbol description min max units mgtavcc analog supply voltage for the gtx transmitter and receiver circuits relative to gnd ?0.5 1.1 v mgtavtt analog supply voltage for the gtx transmitter and receiver termination circuits relative to gnd ?0.5 1.32 v mgtavttrcal analog supply voltage for the resistor cali bration circuit of the gtx transceiver column ?0.5 1.32 v v in receiver (rxp/rxn) and transmitter (t xp/txn) absolute input voltage ?0.5 1.32 v v mgtrefclk reference clock absolute input voltage ?0.5 1.32 v notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not i mplied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. ta bl e 1 4 : recommended operating conditions for gtx transceivers (1)(2) symbol description speed grade pll frequency min typ max units mgtavcc analog supply voltage for the gtx transmitter and receiver circuits relative to gnd -3, -2 (3) > 2.7 ghz 1.0 1.03 1.06 v -3, -2 (3) ? 2.7 ghz 0.95 1.0 1.06 v -1 ? 2.7 ghz 0.95 1.0 1.06 v -1l ? 2.7 ghz 0.95 1.0 1.05 v mgtavtt analog supply voltage for the gtx transmitter and receiver termination circuits relative to gnd all ? 1.14 1.2 1.26 v mgtavttrcal analog supply voltage for the resistor calibration circuit of the gtx transceiver column all ? 1.14 1.2 1.26 v notes: 1. each voltage listed requires the filter circuit described in virtex-6 fpga gtx transceivers user guide . 2. voltages are specified for the temperature range of t j = ?40c to +100c. 3. if a gtx quad contains transceivers operating with a mixture of pll frequencies above and below 2.7 ghz, the mgtavcc voltage s upply must be in the range of 1.0v to 1.06v. ta bl e 1 5 : gtx transceiver supply current (per lane) (1)(2) symbol description typ max units i mgtavtt mgtavtt supply current for one gtx transceiver 55.9 note 2 ma i mgtavcc mgtavcc supply current for one gtx transceiver 56.1 ma mgtr ref precision reference resistor for internal calibration termination 100.0 1% tolerance ? notes: 1. typical values are specified at nominal voltage, 25c, with a 3.125 gb/s line rate. 2. values for currents of other transceiver configurations and conditions can be obtained by using the xpower estimator (xpe) or xpower analyzer (xpa) tools.
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 11 gtx transceiver dc input and output levels ta bl e 1 7 summarizes the dc output specifications of the gtx transceivers in virtex-6 fpgas. consult the virtex-6 fpga gtx transceivers user guide for further details. ta bl e 1 6 : gtx transceiver quiescent supply current (per lane) (1)(2)(3) symbol description typ (4) max units i mgtavttq quiescent mgtavtt supply curre nt for one gtx transceiver 0.9 note 2 ma i mgtavccq quiescent mgtavcc supply current for one gtx transceiver 3.5 ma notes: 1. device powered and unconfigured. 2. currents for conditions other than values specified in this tabl e can be obtained by using the xpower estimator (xpe) or xpow er analyzer (xpa) tools. 3. gtx transceiver quiescent supply current for an entire device can be calculated by multiplying the values in this table by th e number of available gtx transceivers. 4. typical values are specified at nominal voltage, 25c. ta bl e 1 7 : gtx transceiver dc specifications symbol dc parameter conditions min typ max units dv ppin differential peak-to-peak input voltage external ac coupled ? 4.25 gb/s 125 ? 2000 mv external ac coupled > 4.25 gb/s 175 ? 2000 mv v in absolute input voltage dc coupled mgtavtt = 1.2v ?400 ? mgtavtt mv v cmin common mode input voltage dc coupled mgtavtt = 1.2v ? 2/3 mgtavtt ? mv dv ppout differential peak-t o-peak output voltage (1) transmitter output swing is set to maximum setting ? ? 1000 mv v cmoutdc dc common mode output voltage. equation based mgtavtt ? dv ppout /4 mv r in differential input resistance 80 100 130 ? r out differential output resistance 80 100 120 ? t oskew transmitter output pair (txp and txn) intra-pair skew ? 2 8 ps c ext recommended external ac coupling capacitor (2) ? 100 ? nf notes: 1. the output swing and preemphasis levels are programmable using the attributes discussed in the virtex-6 fpga gtx transceivers user guide and can result in values lower than reported in this table. 2. other values can be used as appropriate to conform to specific protocols and standards. x-ref target - figure 1 figure 1: single-ended peak-to-peak voltage 0 +v p n d s 152_01_121509 s ingle-ended volt a ge
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 12 ta bl e 1 8 summarizes the dc specifications of the clock input of the gtx transceiver. consult the virtex-6 fpga gtx transceivers user guide for further details. gtx transceiver switching characteristics consult virtex-6 fpga gtx transceivers user guide for further information. x-ref target - figure 2 figure 2: differential peak-to-peak voltage ta bl e 1 8 : gtx transceiver clock dc input level specification symbol dc parameter conditions min typ max units v idiff differential peak-to-peak input voltage 210 800 2000 mv r in differential input resistance 90 100 130 ? c ext required external ac coupling capacitor ? 100 ? nf ta bl e 1 9 : gtx transceiver performance symbol description speed grade units -3 -2 -1 -1l f gtxmax maximum gtx transceiver data rate 6.6 6.6 5.0 5.0 gb/s f gpllmax maximum pll frequency 3.3 (1) 3.3 (1) 2.7 2.7 ghz f gpllmin minimum pll frequency 1.2 1.2 1.2 1.2 ghz notes: 1. see ta bl e 1 4 for mgtavcc requirements when pll frequency is greater than 2.7 ghz. ta bl e 2 0 : gtx transceiver dynamic reconfiguration port (drp) switching characteristics symbol description speed grade units -3 -2 -1 -1l f gtxdrpclk gtxdrpclk maximum frequency 150 150 125 100 mhz 0 +v ?v p?n d s 152_02_121509 differenti a l volt a ge
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 13 ta bl e 2 1 : gtx transceiver reference clock switching characteristics symbol description conditions all speed grades units min typ max f gclk reference clock frequency range 62.5 ? 650 mhz t rclk reference clock rise time 20% ? 80% ? 200 ? ps t fclk reference clock fall time 80% ? 20% ? 200 ? ps t dcref reference clock duty cycle transceiver pll only 45 50 55 % t lock clock recovery frequency acquisition time initial pll lock ?? 1ms t phase clock recovery phase acquisition time lock to data after pll has locked to the reference clock ??200s x-ref target - figure 3 figure 3: reference clock timing parameters ta bl e 2 2 : gtx transceiver user clock switching characteristics (1) symbol description conditions speed grade units -3 -2 -1 -1l f txout txoutclk maximum frequency internal 20-bit data path 330 330 250 250 mhz internal 16-bit data path 412.5 412.5 312.5 250 mhz f rxrec rxrecclk maximum frequency internal 20-bit data path 330 330 250 250 mhz internal 16-bit data path 412.5 412.5 312.5 250 mhz t rx rxusrclk maximum frequency 412.5 (2) 412.5 (2) 312.5 250 mhz t rx2 rxusrclk2 maximum frequency 1 byte interface 376 376 312.5 250 mhz 2 byte interface 406.25 406.25 312.5 250 mhz 4 byte interface 206.25 206.25 156.25 125 mhz t tx txusrclk maximum frequency 412.5 (3) 412.5 (3) 312.5 250 mhz t tx2 txusrclk2 maximum frequency 1 byte interface 376 376 312.5 250 mhz 2 byte interface 406.25 406.25 312.5 250 mhz 4 byte interface 206.25 206.25 156.25 125 mhz notes: 1. clocking must be implemented as described in the virtex-6 fpga gtx tr ansceivers user guide . 2. 406.25 mhz when the rx elastic buffer is bypassed. 3. 406.25 mhz when the tx buffer is bypassed. d s 152_05_042109 8 0 % 20 % t fclk t rclk
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 14 ta bl e 2 3 : gtx transceiver transmitter switching characteristics symbol description condi tion min typ max units f gtxtx serial data rate range 0.480 ? f gtxmax gb/s t rtx tx rise time 20%?80% ? 120 ? ps t ftx tx fall time 80%?20% ? 120 ? ps t llskew tx lane-to-lane skew (1) ? ? 350 ps v txoobvdpp electrical idle amplitude ? ? 15 mv t txoobtransition electrical idle transition time ? ? 75 ns tj 6.5 total jitter (2)(3) 6.5 gb/s ? ? 0.33 ui dj 6.5 deterministic jitter (2)(3) ? ? 0.17 ui tj 5.0 total jitter (2)(3) 5.0 gb/s ? ? 0.33 ui dj 5.0 deterministic jitter (2)(3) ? ? 0.15 ui tj 4.25 total jitter (2)(3) 4.25 gb/s ? ? 0.33 ui dj 4.25 deterministic jitter (2)(3) ? ? 0.14 ui tj 3.75 total jitter (2)(3) 3.75 gb/s ? ? 0.34 ui dj 3.75 deterministic jitter (2)(3) ? ? 0.16 ui tj 3.125 total jitter (2)(3) 3.125 gb/s ??0.2ui dj 3.125 deterministic jitter (2)(3) ??0.1ui tj 3.125l total jitter (2)(3) 3.125 gb/s (4) ? ? 0.35 ui dj 3.125l deterministic jitter (2)(3) ? ? 0.16 ui tj 2.5 total jitter (2)(3) 2.5 gb/s (5) ? ? 0.20 ui dj 2.5 deterministic jitter (2)(3) ? ? 0.08 ui tj 1.25 total jitter (2)(3) 1.25 gb/s (6) ? ? 0.15 ui dj 1.25 deterministic jitter (2)(3) ? ? 0.06 ui tj 600 total jitter (2)(3) 600 mb/s ??0.1ui dj 600 deterministic jitter (2)(3) ? ? 0.03 ui tj 480 total jitter (2)(3) 480 mb/s ??0.1ui dj 480 deterministic jitter (2)(3) ? ? 0.03 ui notes: 1. using same refclk input with txenpmaphasealign enabled for up to 12 consecutive transmitters (three fully populated gtx quads ). 2. using pll_divsel_fb = 2, 20-bit internal data width. these values are not intended for protocol specific compliance determinati ons. 3. all jitter values are based on a bit-error ratio of 1e -12 . 4. pll frequency at 1.5625 ghz and outdiv = 1. 5. pll frequency at 2.5 ghz and outdiv = 2. 6. pll frequency at 2.5 ghz and outdiv = 4.
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 15 ta bl e 2 4 : gtx transceiver receiver switching characteristics symbol description min typ max units f gtxrx serial data rate rx oversampler not enabled 0.600 ? f gtxmax gb/s rx oversampler enabled 0.480 ? 0.600 gb/s t rxelecidle time for rxelecidle to respond to loss or restoration of data ?75 ? ns rx oobvdpp oob detect threshold peak-to-peak 60 ? 150 mv rx sst receiver spread-spectrum tracking (1) modulated @ 33 khz ?5000 ? 0 ppm rx rl run length (cid) internal ac capacitor bypassed ? ? 512 ui rx ppmtol data/refclk ppm offset tolerance cdr 2 nd -order loop disabled ?200 ? 200 ppm cdr 2 nd -order loop enabled ?2000 ? 2000 ppm sj jitter tolerance (2) jt_sj 6.5 sinusoidal jitter (3) 6.5 gb/s 0.44 ? ? ui jt_sj 5.0 sinusoidal jitter (3) 5.0 gb/s 0.44 ? ? ui jt_sj 4.25 sinusoidal jitter (3) 4.25 gb/s 0.44 ? ? ui jt_sj 3.75 sinusoidal jitter (3) 3.75 gb/s 0.44 ? ? ui jt_sj 3.125 sinusoidal jitter (3) 3.125 gb/s 0.45 ? ? ui jt_sj 3.125l sinusoidal jitter (3) 3.125 gb/s (4) 0.45 ? ? ui jt_sj 2.5 sinusoidal jitter (3) 2.5 gb/s (5) 0.5 ? ? ui jt_sj 1.25 sinusoidal jitter (3) 1.25 gb/s (6) 0.5 ? ? ui jt_sj 600 sinusoidal jitter (3) 600 mb/s 0.4 ? ? ui jt_sj 480 sinusoidal jitter (3) 480 mb/s 0.4 ? ? ui sj jitter tolerance with stressed eye (2) jt_tjse 3.125 total jitter wi th stressed eye (7) 3.125 gb/s 0.70 ? ? ui 5.0 gb/s 0.70 ? ? ui jt_sjse 3.125 sinusoidal jitter with stressed eye (7) 3.125 gb/s 0.1 ? ? ui 5.0 gb/s 0.1 ? ? ui notes: 1. using pll_rxdivsel_out = 1, 2, and 4. 2. all jitter values are based on a bit error ratio of 1e ?12 . 3. the frequency of the injected sinusoidal jitter is 80 mhz. 4. pll frequency at 1.5625 ghz and outdiv = 1. 5. pll frequency at 2.5 ghz and outdiv = 2. 6. pll frequency at 2.5 ghz and outdiv = 4. 7. composite jitter with rx equalizer enabled. dfe disabled.
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 16 gth transceiver specifications gth transceiver dc characteristics ta bl e 2 5 : absolute maximum ratings for gth transceivers (1) symbol description min max units mgthavcc analog supply voltage for the gth transmitter, receiver, and common analog circuits ?0.5 v mgthavccrx analog supply voltage for the gth rece iver circuits and common analog circuits ?0.5 v mgthavtt analog supply voltage for the gth transmitter termination circuits ?0.5 v mgthavccpll analog supply voltage for the gth receiver and pll circuits ?0.5 v v in receiver (rxp/rxn) and transmitter (txp/txn) absolute input voltage ?0.5 v v mgtrefclk reference clock absolute input voltage ?0.5 v notes: 1. stresses beyond those listed under absolute maximum ratings might cause permanent damage to the device. these are stress rati ngs only, and functional operation of the device at these or any other conditions beyond those listed under operating conditions is not i mplied. exposure to absolute maximum ratings conditions for extended periods of time might affect device reliability. ta bl e 2 6 : recommended operating conditions for gth transceivers (1)(2) symbol description min typ max units mgthavcc analog supply voltage for the gth transmitter, receiver, and common analog circuits 1.075 1.1 1.125 v mgthavccrx analog supply voltage for the gth receiver circuits and common analog circuits 1.075 1.1 1.125 v mgthavtt analog supply voltage for the gth transmitter termination circuits 1.140 1.2 1.26 v mgthavccpll analog supply voltage for the gth receiver and pll circuit 1.710 1.8 1.89 v notes: 1. each voltage listed requires the filter circuit described in virtex-6 fpga gth transceivers user guide . 2. voltages are specified for the temperature range of t j = ?40c to +100c. ta bl e 2 7 : gth transceiver power supply sequencing (1)(2) symbol description min max units t havcc2havccrx maximum time between powering mgthavcc to when mgthavccrx must be powered. 0200s t havccrx2havccpll minimum time between powering mgthavccrx to when mgthavccpll can be powered. 10 ? s t havccrx2havtt minimum time between powering mgthavccrx to when mgthavtt can be powered. 10 ? s notes: 1. mgthavccrx must be powered simultaneously or within t havcc2havccrx of mgthavcc, but it must not precede mgthavcc. 2. mgthavcc and mgthavccrx must be powered before mgthavcc pll and mgthavtt. this mini mum time is defined by t havccrx2havccpll and t havccrx2havtt .
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 17 figure 4 shows the timing parameters in ta bl e 2 7 . x-ref target - figure 4 figure 4: gth transceiver power supply power-on sequencing ta bl e 2 8 : gth transceiver supply current (1)(2) symbol description min typ max units i mgthavcc mgthavcc supply current for one gth quad (4 lanes) ma i mgthavccrx mgthavccrx supply current for a gth quad (4 lanes) ma i mgthavtt mgthavtt supply current for one gth quad (4 lanes) ma i mgthavccpll mgthavccpll supply current for one gth quad (4 lanes) ma mgtr ref precision reference resistor for internal calibration termination 1000.0 1% tolerance ? notes: 1. typical values are specified at nominal voltage, 25c, with a 10.3125 gb/s line rate. 2. values for currents other than the values specified in this table can be obtained by using the xpower estimator (xpe) or xpow er analyzer (xpa) tools. ta bl e 2 9 : gth transceiver quiescent supply current (1)(2)(3) symbol description typ (4) max units i mgthavccq quiescent mgthavcc supply current for one gth quad (4 lanes) ma i mgthavccrxq quiescent mgthavccrx supply current for one gth quad (4 lanes) ma i mgthavttq quiescent mgthavtt supply current for one gth quad (4 lanes) ma i mgthavccpllq quiescent mgthavccpll supply current for one gth quad (4 lanes) ma notes: 1. device powered and unconfigured. 2. currents for conditions other than values specified in this tabl e can be obtained by using the xpower estimator (xpe) or xpow er analyzer (xpa) tools. 3. gth transceiver quiescent supply current for an entire device can be calculated by multiplying the values in this table by th e number of available gth transceivers. 4. typical values are specified at nominal voltage, 25c. mgthavcc (1.1v dc) mgthavccpll (1. 8 v dc) mgthavccrx (1.1v dc) mgthavtt (1.2v dc) t havcc2havccrx t havccrx2havccpll t havccrx2havtt d s 152_04_051110
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 18 gth transceiver dc input and output levels ta bl e 3 0 summarizes the dc output specifications of the gth transceivers in virtex-6 fpgas. consult the virtex-6 fpga gth transceivers user guide for further details. ta bl e 3 1 summarizes the dc specifications of the clock input of the gth transceiver. consult the virtex-6 fpga gth transceivers user guide for further details. ta bl e 3 0 : gth transceiver dc specifications symbol dc parameter conditions min typ max units d vppin differential peak-to-peak input voltage external ac coupled mv d vppout differential peak-to-peak output voltage (1) transmitter output swing is set to maximum setting mv r in differential input resistance 100 ? r out differential output resistance 100 ? t oskew transmitter output pair (txp and txn) intra-pair skew ps c ext recommended external ac coupling capacitor (2) 100 nf notes: 1. the output swing and preemphasis levels are programmable using the attributes discussed in the virtex-6 fpga gth transceivers user guide and can result in values lower than reported in this table. 2. other values can be used as appropriate to conform to specific protocols and standards. ta bl e 3 1 : gth transceiver clock dc input level specification symbol dc parameter conditions min typ max units v idiff differential peak-to-peak input voltage ? 600 mhz 500 1600 mv > 600 mhz 600 1600 mv r in differential input resistance 100 ? c ext required external ac coupling capacitor 100 nf
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 19 gth transceiver switching characteristics consult virtex-6 fpga gth transceivers user guide for further information. ta bl e 3 2 : gth transceiver maximum data rate and pll frequency range symbol description conditions speed grade units -3 -2 -1 f gthmax maximum gth transceiver data rate pll output divider = 1 11.182 11.182 10.32 gb/s pll output divider = 4 2.795 2.795 2.58 gb/s f gthmin minimum gth transceiver data rate (1) pll output divider = 1 9.92 9.92 9.92 gb/s pll output divider = 4 2.48 2.48 2.48 gb/s f gpllmax maximum gth pll frequency 5.591 5.591 5.16 ghz f gpllmin minimum gth pll frequency 4.96 4.96 4.96 ghz notes: 1. lower data rates can be achieved using fpga logic based oversampling designs. ta bl e 3 3 : gth transceiver dynamic reconfiguration port (drp) switching characteristics symbol description speed grade units -3 -2 -1 f gthdrpclk gthdrpclk maximum frequency 70 70 60 mhz ta bl e 3 4 : gth transceiver reference clock switching characteristics symbol description conditions all speed grades units min typ max f gclk reference clock frequency range -1 speed grade 150 623 mhz -2 and -3 speed grades 150 670 mhz t rclk reference clock rise time 20% ? 80% 200 ps t fclk reference clock fall time 80% ? 20% 200 ps t dcref reference clock duty cycle clk 45 50 55 % t lock clock recovery frequency acquisition time initial pll lock ms t phase clock recovery phase acquisition time lock to data after pll has locked to the reference clock s x-ref target - figure 5 figure 5: reference clock timing parameters d s 152_05_042109 8 0 % 20 % t fclk t rclk
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 20 ta bl e 3 5 : gth transceiver user clock switching characteristics (1) symbol descripti on conditions speed grade units -3 -2 -1 f txout txuserclkout maximum frequency 350 350 323 mhz f rxout rxuserclkout maximum frequency 350 350 323 mhz f txin txuserclkin maximum frequency 16-bit data path 350 350 323 mhz 20-bit data path 280 280 258 mhz 32-bit data path 350 350 323 mhz 40-bit data path 280 280 258 mhz 64-bit data path 175 175 162 mhz 80-bit data path 140 140 129 mhz 64b/66b-bit data path 170 170 157 mhz f rxin rxuserclkin maximum frequency 16-bit data path 350 350 323 mhz 20-bit data path 280 280 258 mhz 32-bit data path 350 350 323 mhz 40-bit data path 280 280 258 mhz 64-bit data path 175 175 162 mhz 80-bit data path 140 140 129 mhz 64b/66b-bit data path 170 170 157 mhz notes: 1. clocking must be implemented as described in the virtex-6 fpga gth tr ansceivers user guide . ta bl e 3 6 : gth transceiver transmitter switching characteristics symbol description condi tion min typ max units t rtx tx rise time 20%?80% ps t ftx tx fall time 80%?20% ps t llskew tx lane-to-lane skew within one gth quad ps across multiple gth quads ps transmitter output jitter (1)(2)(3) tj 11.18 total jitter 11.181 gb/s 0.3 ui dj 11.18 deterministic jitter ui tj 10.3125 total jitter 10.3125 gb/s 0.3 ui dj 10.3125 deterministic jitter ui tj 9.953 total jitter 9.953 gb/s 0.3 ui dj 9.953 deterministic jitter ui tj 2.667 total jitter 2.667 gb/s ui dj 2.667 deterministic jitter ui tj 2.488 total jitter 2.488 gb/s ui dj 2.488 deterministic jitter ui notes: 1. these values are not intended for protocol specific compliance determinations. 2. all jitter values are based on a bit-error ratio of 1e -12 . 3. using prbs15 pattern.
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 21 ethernet mac switching characteristics consult virtex-6 fpga embedded tri-mode ethernet mac user guide for further information. ta bl e 3 7 : gth transceiver receiver switching characteristics symbol description min typ max units r xrl run length (cid) ui r xppmtol data/refclk ppm offset tolerance ?200 200 ppm sj jitter tolerance (1)(2)(3)(4) jt_sj 11.18 sinusoidal jitter 11.18 gb/s 0.3 ui jt_sj 10.32 sinusoidal jitter 10.32 gb/s 0.3 ui jt_sj 9.95 sinusoidal jitter 9.95 gb/s 0.3 ui jt_sj 2.667 sinusoidal jitter 2.667 gb/s ui jt_sj 2.48 sinusoidal jitter 2.48 gb/s ui notes: 1. these values are not intended for protocol specific compliance determinations. 2. all jitter values are based on a bit error ratio of 1e ?12 . 3. the frequency of the injected sinusoidal jitter is 80 mhz. 4. high frequency jitter tolerance including 6 db channel. ta bl e 3 8 : maximum ethernet mac performance symbol description conditions speed grade units -3 -2 -1 -1l f temacclient client interface maximum frequency 10 mb/s ? 8-bit width 2.5 (1) 2.5 (1) 2.5 (1) 2.5 (1) mhz 100 mb/s ? 8-bit width 25 (2) 25 (2) 25 (2) 25 (2) mhz 1000 mb/s ? 8-bit width 125 125 125 125 mhz 1000 mb/s ? 16-bit width 62.5 62.5 62.5 62.5 mhz 2000 mb/s ? 16-bit width 125 125 125 n/a mhz 2500 mb/s ? 16-bit width 156.25 156.25 156.25 n/a mhz f temacphy physical interface maximum frequency 10 mb/s ? 4-bit width 2.5 2.5 2.5 2.5 mhz 100 mb/s ? 4-bit width 25 25 25 25 mhz 1000 mb/s ? 8-bit width 125 125 125 125 mhz 2000 mb/s ? 8-bit width 250 250 250 n/a mhz 2500 mb/s ? 8-bit width 312.5 312.5 312.5 n/a mhz notes: 1. when not using clock enable, the f max is lowered to 1.25 mhz. 2. when not using clock enable, the f max is lowered to 12.5 mhz.
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 22 integrated interface block for pci ex press designs switching characteristics more information and documentation on soluti ons for pci express designs can be found at: http://www.xilinx.com /technology/protoco ls/pciexpress.htm system monitor analog-to-digit al converter specification ta bl e 3 9 : maximum performance for pci express designs symbol description speed grade units -3 -2 -1 -1l f pipeclk pipe clock maximum frequency 250 250 250 250 mhz f userclk user clock maximum frequency 500 500 250 250 mhz f drpclk drp clock maximum frequency 250 250 250 250 mhz ta bl e 4 0 : analog-to-digital specifications parameter symbol comments/conditions min typ max units av dd =2.5v5%, v refp = 1.25v, v refn = 0v, adcclk = 5.2 mhz, t j = ?40c to 100c, typical values at t j =+35c dc accuracy: all external input channels. both unipolar and bipolar modes. resolution 10 ? ? bits integral nonlinearity inl ? ? 1 lsbs differential nonlinearity dnl no missing codes (t min to t max ) guaranteed monotonic ? ? 0.9 lsbs unipolar offset error (1) uncalibrated ? 2 30 lsbs bipolar offset error (1) uncalibrated measured in bipolar mode ? 2 30 lsbs gain error uncalibrated - external reference ? 0.2 2 % uncalibrated - internal reference ? 2 ? % bipolar gain error (1) uncalibrated - external reference ? 0.2 2 % uncalibrated - internal reference ? 2 ? % total unadjusted error (uncalibrated) tue deviation from ideal transfer function. external 1.25v reference ? 10 ? lsbs deviation from ideal transfer function. internal reference ? 20 ? lsbs total unadjusted error (calibrated) tue deviation from ideal transfer function. external 1.25v reference ? 1 2 lsbs calibrated gain temperature coefficient variation of fs code with temperature ? 0.01 ? lsb/c dc common-mode reject cmrr dc v n = v cm = 0.5v 0.5v, v p ?v n = 100mv ?70 ? db conversion rate (2) conversion time - continuous t conv number of clk cycles 26 ? 32 conversion time - event t conv number of clk cycles ? ? 21 t/h acquisition time t acq number of clk cycles 4 ? ? drp clock frequency dclk drp clock frequency 8 ? 80 mhz adc clock frequency adcclk derived from dclk 1 ? 5.2 mhz clk duty cycle 40 ? 60 %
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 23 analog inputs (3) dedicated analog inputs input voltage range v p - v n unipolar operation 0 ? 1 volts bipolar operation ?0.5 ? +0.5 unipolar common mode range (fs input) 0 ? +0.5 bipolar common mode range (fs input) +0.5 ? +0.6 bandwidth ? 20 ? mhz auxiliary analog inputs input voltage range v auxp[0] /v auxn[0] to v auxp[15] /v auxn[15] t j = ?40c to 100c unipolar operation 0 ? 1 volts bipolar operation ?0.5 ? +0.5 unipolar common mode range (fs input) 0 ? +0.5 bipolar common mode range (fs input) +0.5 ? +0.6 bandwidth ? 10 ? khz input leakage current a/d not converting, adcclk stopped ? 1.0 ? a input capacitance ?10 ? pf on-chip supply monitor error v ccint and v ccaux with calibration enabled. external 1.25v reference t j = ?40c to 125c. ? ? 1.0 % reading v ccint and v ccaux with calibration enabled. internal reference t j = ?40c to 100c. ? 2 ? % reading on-chip temperature monitor error t j = ?40c to +125c with calibration enabled. external 1.25v reference. ??4 c t j = ?40c to +100c with calibration enabled. internal reference. ?5 ? c external reference inputs (4) positive reference input voltage range v refp measured relative to v refn 1.20 1.25 1.30 volts negative reference input voltage range v refn measured relative to agnd ?50 0 100 mv input current i ref adcclk = 5.2 mhz ? ? 100 a power requirements analog power supply av dd measured relative to av ss 2.375 2.5 2.625 volts analog supply current ai dd adcclk = 5.2 mhz ? ? 12 ma notes: 1. offset errors are removed by enabling the system monitor automatic gain calibration feature. 2. see "system monitor timing" in the virtex-6 fpga system monitor user guide 3. see "analog inputs" in the virtex-6 fpga system monitor user guide for a detailed description. 4. any variation in the reference voltage from the nominal v refp = 1.25v and v refn = 0v will result is a deviation from the ideal transfer function.this also impacts the accuracy of the internal sensor measurements (i.e., temperature and power supply). however, for external ratiometric type applications allowing reference to vary by 4% is permitted. ta bl e 4 0 : analog-to-digital specifications (cont?d) parameter symbol comments/conditions min typ max units
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 24 performance characteristics this section provides the performance characteristics of some common functions and designs implemented in virtex-6 devices. the numbers reported here are worst-case values; they have all been fully characterized. these values are subject to the same guidelines as the switching characteristics, page 25 . ta bl e 4 1 : interface performances description speed grade -3 -2 -1 -1l networking applications sdr lvds transmitter (using oserdes; data_width = 4 to 8) 710 mb/s 710 mb/s 650 mb/s 585 mb/s ddr lvds transmitter (using oserdes; data_w idth = 4 to 10) 1.4 gb/s 1.3 gb/s 1.25 gb/s 1.1 gb/s sdr lvds receiver (sfi-4.1) (1) 710 mb/s 710 mb/s 650 mb/s 585 mb/s ddr lvds receiver (spi-4.2) (1) 1.4 gb/s 1.3 gb/s 1.0 gb/s 0.9 gb/s maximum physical interface (phy) rate for memory interfaces (2)(3) ddr2 800 mb/s 800 mb/s 800 mb/s 606 mb/s ddr3 1066 mb/s 1066 mb/s 800 mb/s 606 mb/s qdr ii + sram 400 mhz 350 mhz 300 mhz ? rldram ii 500 mhz 400 mhz 350 mhz ? notes: 1. lvds receivers are typically bounded with certain applications where specific dpa algorithms dominate deterministic performan ce. 2. verified on xilinx memory characterization platforms designed according to the guidelines in the virtex-6 fpga memory interface solutions user guide . 3. consult the virtex-6 fpga memory interface solutions data sheet for performance and feature information on memory interface cores (controller plus phy).
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 25 switching characteristics all values represented in this data sheet are based on these speed specifications: v1.10 for -3, -2, and -1; and v1.07 for -1l. switching characteristics are specified on a per-speed- grade basis and can be designated as advance, preliminary, or production. each designation is defined as follows: advance these specifications are based on simulations only and are typically available soon after device design specifications are frozen. although speed grades with this designation are considered relatively stable and conservative, some under- reporting might still occur. preliminary these specifications are based on complete es (engineering sample) silicon characterization. devices and speed grades with this designation are intended to give a better indication of the expected performance of production silicon. the probability of under -reporting delays is greatly reduced as compared to advance data. production these specifications are released once enough production silicon of a particular device family member has been characterized to provide full correlation between specifications and devices over numerous production lots. there is no under-reporting of delays, and customers receive formal notification of any subsequent changes. typically, the slowest speed grades transition to production before faster speed grades. all specifications are always representative of worst-case supply voltage and junction temperature conditions. since individual family members are produced at different times, the migration from one category to another depends completely on the status of the fabrication process for each device. ta b l e 4 2 correlates the current status of each virtex-6 device on a per speed grade basis. testing of switching characteristics all devices are 100% functionally tested. internal timing parameters are derived from measuring internal test patterns. listed below are representative values. for more specific, more precise, and worst-case guaranteed data, use the values reported by the static timing analyzer and back-annotate to the simulation net list. unless otherwise noted, values apply to all virtex-6 devices. ta b l e 4 2 : virtex-6 device speed grade designations device speed grade designations advance preliminary production xc6vlx75t -3, -2, -1, -1l xc6vlx130t -3, -2, -1, -1l xc6vlx195t -3, -2, -1, -1l xc6vlx240t -3, -2, -1, -1l xc6vlx365t -3, -2, -1, -1l xc6vlx550t -2, -1, -1l xc6vlx760 -2, -1, -1l xc6vsx315t -3, -2, -1, -1l xc6vsx475t -2, -1, -1l xc6vhx250t -3, -2, -1 xc6vhx255t -3, -2, -1 xc6vhx380t -3, -2, -1 xc6vhx565t -2, -1
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 26 production silicon and ise software status in some cases, a particular family member (and speed grade) is released to production before a speed specification is released with the correct label (advance, preliminary, production). any labeling discrepancies are corrected in subsequent speed specification releases. ta b l e 4 3 lists the production released virtex-6 family member, speed grade, and the minimum corresponding supported speed specification version and ise software revisions. the ise? software and speed specifications listed are the minimum releases required for production. all subsequent releases of softwa re and speed specifications are valid. iob pad input/output/3-state switching characteristics ta bl e 4 4 summarizes the values of standard-specific data input delay adjustments, output delays terminating at pads (based on standard) and 3-state delays. t iopi is described as the delay from iob pad through the input buffer to the i-pin of an iob pad. the delay varies depending on th e capability of the selectio input buffer. t ioop is described as the delay from the o pin to the iob pad through the output buffer of an iob pad. the delay varies depending on the capability of th e selectio output buffer. t iotp is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is disabled. the delay varies depending on the selectio capability of the output buffer. ta b l e 4 5 summarizes the value of t iotphz . t iotphz is described as the delay from the t pin to the iob pad through the output buffer of an iob pad, when 3-state is enabled (i.e., a high impedance state). ta bl e 4 3 : virtex-6 device production software and speed specification release device speed grade designations -3 -2 -1 -1l xc6vlx75t ise 12.2 v1.08 ise 12.3 v1.07 patch xc6vlx130t ise 12.1 v1.06 ise 11.5 v1.05 (2) ise 11.5 v1.05 (2) ise 12.2 v1.05 xc6vlx195t ise 12.1 v1.06 ise 12.1 v1.06 ise 12.1 v1.06 ise 12.2 v1.04 xc6vlx240t ise 12.1 v1.06 ise 11.4.1 v1.04 (2) ise 11.4.1 v1.04 (2) ise 12.2 v1.04 xc6vlx365t ise 12.2 v1.08 ise 12.2 v1.04 xc6vlx550t n/a ise 12.2 v1.07 ise 12.2 v1.04 xc6vlx760 n/a ise 12.2 v1.08 ise 12.3 v1.07 patch xc6vsx315t ise 12.2 v1.08 ise 12 .1 v1.06 ise 12.3 v1.07 patch xc6vsx475t n/a ise 12.2 v1 .08 ise 12.3 v1.07 patch xc6vhx250t ise 12.4 v1.10 n/a xc6vhx255t n/a xc6vhx380t n/a xc6vhx565t n/a n/a notes: 1. blank entries indicate a device and/or speed grade in advance or preliminary status. 2. designs utilizing the gtx transceivers must use the software version ise 12.1 v1.06 or later. ta bl e 4 4 : iob switching characteristics i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1 -1l -3 -2 -1 -1l -3 -2 -1 -1l lvds_25 0.85 0.94 1.09 1.08 1.45 1. 54 1.68 1.62 1.45 1.54 1.68 1.62 ns lvdsext_25 0.85 0.94 1.09 1.08 1.53 1 .65 1.84 1.73 1.53 1.65 1.84 1.73 ns
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 27 ht_25 0.85 0.94 1.09 1. 08 1.51 1.62 1.78 1.69 1.51 1.62 1.78 1.69 ns blvds_25 0.85 0.94 1.09 1.08 1.39 1. 50 1.67 1.65 1.39 1.50 1.67 1.65 ns rsds_25 (point to point) 0.85 0.94 1.09 1 .08 1.45 1.54 1.68 1.62 1 .45 1.54 1.68 1.62 ns hstl_i 0.81 0.91 1.06 1. 06 1.45 1.56 1.73 1.71 1.45 1.56 1.73 1.71 ns hstl_ii 0.81 0.91 1.06 1.06 1.44 1.5 61.741.721.441.561.741.72 ns hstl_iii 0.81 0.91 1.06 1.06 1.42 1.54 1.71 1.69 1.42 1.54 1.71 1.69 ns hstl_i_18 0.81 0.91 1.06 1.06 1.47 1.58 1.75 1.72 1.47 1.58 1.75 1.72 ns hstl_ii_18 0.81 0.91 1. 06 1.06 1.50 1.62 1.81 1. 78 1.50 1.62 1.81 1.78 ns hstl_iii_18 0.81 0.91 1.06 1.06 1.42 1 .54 1.71 1.69 1.42 1.54 1.71 1.69 ns sstl2_i 0.81 0.91 1.06 1.06 1.49 1. 60 1.77 1.74 1.49 1.60 1.77 1.74 ns sstl2_ii 0.81 0.91 1.06 1.06 1.42 1.5 41.721.711.421.541.721.71 ns sstl15 0.81 0.91 1.06 1.06 1.42 1.5 41.711.691.421.541.711.69 ns lvcmos25, slow, 2 ma 0.51 0.57 0.66 0.70 5 .09 5.46 6.01 5.63 5.09 5.46 6.01 5.63 ns lvcmos25, slow, 4 ma 0.51 0.57 0.66 0.70 3 .30 3.49 3.79 3.65 3.30 3.49 3.79 3.65 ns lvcmos25, slow, 6 ma 0.51 0.57 0.66 0.70 2 .62 2.81 3.08 2.95 2.62 2.81 3.08 2.95 ns lvcmos25, slow, 8 ma 0.51 0.57 0.66 0.70 2 .21 2.41 2.72 2.59 2.21 2.41 2.72 2.59 ns lvcmos25, slow, 12 ma 0.51 0.57 0.66 0.70 1.80 1.95 2.17 2.10 1. 80 1.95 2.17 2.10 ns lvcmos25, slow, 16 ma 0.51 0.57 0.66 0.70 1.89 2.05 2.29 2.21 1. 89 2.05 2.29 2.21 ns lvcmos25, slow, 24 ma 0.51 0.57 0.66 0.70 1.68 1.82 2.02 1.98 1. 68 1.82 2.02 1.98 ns lvcmos25, fast, 2 ma 0.51 0.57 0.66 0.70 5 .12 5.49 6.04 5.62 5.12 5.49 6.04 5.62 ns lvcmos25, fast, 4 ma 0.51 0.57 0.66 0.70 3 .28 3.50 3.82 3.65 3.28 3.50 3.82 3.65 ns lvcmos25, fast, 6 ma 0.51 0.57 0.66 0.70 2 .56 2.73 2.99 2.88 2.56 2.73 2.99 2.88 ns lvcmos25, fast, 8 ma 0.51 0.57 0.66 0.70 2 .11 2.33 2.65 2.53 2.11 2.33 2.65 2.53 ns lvcmos25, fast, 12 ma 0.51 0.57 0.66 0.70 1.74 1.88 2.08 2.03 1. 74 1.88 2.08 2.03 ns lvcmos25, fast, 16 ma 0.51 0.57 0.66 0.70 1.77 1.92 2.13 2.08 1. 77 1.92 2.13 2.08 ns lvcmos25, fast, 24 ma 0.51 0.57 0.66 0.70 1.66 1.79 1.99 1.96 1. 66 1.79 1.99 1.96 ns lvcmos18, slow, 2 ma 0.55 0.61 0.71 0.73 4 .21 4.47 4.87 4.30 4.21 4.47 4.87 4.30 ns lvcmos18, slow, 4 ma 0.55 0.61 0.71 0.73 2 .79 2.96 3.21 2.94 2.79 2.96 3.21 2.94 ns lvcmos18, slow, 6 ma 0.55 0.61 0.71 0.73 2 .30 2.43 2.64 2.47 2.30 2.43 2.64 2.47 ns lvcmos18, slow, 8 ma 0.55 0.61 0.71 0.73 2 .01 2.11 2.27 2.24 2.01 2.11 2.27 2.24 ns lvcmos18, slow, 12 ma 0.55 0.61 0.71 0.73 1.88 1.99 2.15 2.10 1. 88 1.99 2.15 2.10 ns lvcmos18, slow, 16 ma 0.55 0.61 0.71 0.73 1.84 1.95 2.11 2.04 1. 84 1.95 2.11 2.04 ns lvcmos18, fast, 2 ma 0.55 0.61 0.71 0.73 4 .00 4.23 4.57 4.08 4.00 4.23 4.57 4.08 ns lvcmos18, fast, 4 ma 0.55 0.61 0.71 0.73 2 .62 2.76 2.97 2.74 2.62 2.76 2.97 2.74 ns lvcmos18, fast, 6 ma 0.55 0.61 0.71 0.73 2 .15 2.28 2.46 2.32 2.15 2.28 2.46 2.32 ns lvcmos18, fast, 8 ma 0.55 0.61 0.71 0.73 1 .90 1.99 2.13 2.14 1.90 1.99 2.13 2.14 ns lvcmos18, fast, 12 ma 0.55 0.61 0.71 0.73 1.69 1.80 1.97 1.88 1. 69 1.80 1.97 1.88 ns lvcmos18, fast, 16 ma 0.55 0.61 0.71 0.73 1.63 1.74 1.91 1.88 1. 63 1.74 1.91 1.88 ns ta bl e 4 4 : iob switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1 -1l -3 -2 -1 -1l -3 -2 -1 -1l
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 28 lvcmos15, slow, 2 ma 0.64 0.73 0.85 0.85 3 .43 3.77 4.29 3.91 3.43 3.77 4.29 3.91 ns lvcmos15, slow, 4 ma 0.64 0.73 0.85 0.85 2 .58 2.79 3.10 2.93 2.58 2.79 3.10 2.93 ns lvcmos15, slow, 6 ma 0.64 0.73 0.85 0.85 2 .08 2.32 2.68 2.50 2.08 2.32 2.68 2.50 ns lvcmos15, slow, 8 ma 0.64 0.73 0.85 0.85 1 .81 1.98 2.23 2.24 1.81 1.98 2.23 2.24 ns lvcmos15, slow, 12 ma 0.64 0.73 0.85 0.85 1.76 1.91 2.13 2.07 1. 76 1.91 2.13 2.07 ns lvcmos15, slow, 16 ma 0.64 0.73 0.85 0.85 1.69 1.83 2.04 1.98 1. 69 1.83 2.04 1.98 ns lvcmos15, fast, 2 ma 0.64 0.73 0.85 0.85 3 .44 3.77 4.28 3.91 3.44 3.77 4.28 3.91 ns lvcmos15, fast, 4 ma 0.64 0.73 0.85 0.85 2 .37 2.53 2.78 2.66 2.37 2.53 2.78 2.66 ns lvcmos15, fast, 6 ma 0.64 0.73 0.85 0.85 1 .80 2.05 2.42 2.16 1.80 2.05 2.42 2.16 ns lvcmos15, fast, 8 ma 0.64 0.73 0.85 0.85 1 .76 1.90 2.11 2.04 1.76 1.90 2.11 2.04 ns lvcmos15, fast, 12 ma 0.64 0.73 0.85 0.85 1.64 1.77 1.97 1.90 1. 64 1.77 1.97 1.90 ns lvcmos15, fast, 16 ma 0.64 0.73 0.85 0.85 1.62 1.76 1.96 1.92 1. 62 1.76 1.96 1.92 ns lvcmos12, slow, 2 ma 0.72 0.81 0.93 0.95 3 .14 3.39 3.75 3.54 3.14 3.39 3.75 3.54 ns lvcmos12, slow, 4 ma 0.72 0.81 0.93 0.95 2 .43 2.63 2.93 2.79 2.43 2.63 2.93 2.79 ns lvcmos12, slow, 6 ma 0.72 0.81 0.93 0.95 1 .92 2.11 2.41 2.26 1.92 2.11 2.41 2.26 ns lvcmos12, slow, 8 ma 0.72 0.81 0.93 0.95 1 .87 2.02 2.25 2.17 1.87 2.02 2.25 2.17 ns lvcmos12, fast, 2 ma 0.72 0.81 0.93 0.95 2 .71 2.98 3.39 3.11 2.71 2.98 3.39 3.11 ns lvcmos12, fast, 4 ma 0.72 0.81 0.93 0.95 1 .93 2.16 2.51 2.31 1.93 2.16 2.51 2.31 ns lvcmos12, fast, 6 ma 0.72 0.81 0.93 0.95 1 .75 1.89 2.11 2.05 1.75 1.89 2.11 2.05 ns lvcmos12, fast, 8 ma 0.72 0.81 0.93 0.95 1 .69 1.82 2.02 1.98 1.69 1.82 2.02 1.98 ns lvdci_25 0.51 0.57 0.66 0. 70 2.05 2.14 2.26 2.26 2.05 2.14 2.26 2.26 ns lvdci_18 0.55 0.61 0.71 0. 73 2.07 2.23 2.47 2.38 2.07 2.23 2.47 2.38 ns lvdci_15 0.64 0.73 0.85 0. 85 1.85 2.01 2.24 2.18 1.85 2.01 2.24 2.18 ns lvdci_dv2_25 0.51 0.57 0.66 0.70 1.71 1 .83 2.01 2.00 1.71 1.83 2.01 2.00 ns lvdci_dv2_18 0.55 0.61 0.71 0.73 1.69 1 .81 2.00 1.98 1.69 1.81 2.00 1.98 ns lvdci_dv2_15 0.64 0.73 0.85 0.85 1.68 1 .77 1.91 1.98 1.68 1.77 1.91 1.98 ns lvpecl_25 0.85 0.94 1.09 1.08 1.38 1.4 9 1.65 1.64 1.38 1.49 1.65 1.64 ns hstl_i_12 0.81 0.91 1.06 1.06 1.48 1.60 1.78 1.74 1.48 1.60 1.78 1.74 ns hstl_i_dci 0.81 0.91 1. 06 1.06 1.40 1.50 1.66 1. 64 1.40 1.50 1.66 1.64 ns hstl_ii_dci 0.81 0.91 1. 06 1.06 1.37 1.49 1.68 1. 66 1.37 1.49 1.68 1.66 ns hstl_ii_t_dci 0.81 0.91 1. 06 1.06 1.40 1.50 1.66 1. 64 1.40 1.50 1.66 1.64 ns hstl_iii_dci 0.81 0.91 1. 06 1.06 1.34 1.45 1.62 1. 61 1.34 1.45 1.62 1.61 ns hstl_i_dci_18 0.81 0.91 1.06 1.06 1.4 21.531.681.661.421.531.681.66 ns hstl_ii_dci_18 0.81 0.91 1. 06 1.06 1.36 1.46 1.62 1. 59 1.36 1.46 1.62 1.59 ns hstl_ii _t_dci_18 0.81 0.91 1.06 1.06 1 .42 1.53 1.68 1.66 1.42 1.53 1.68 1.66 ns hstl_iii_dci_18 0.81 0.91 1.06 1.06 1.4 31.541.691.671.431.541.691.67 ns diff_hstl_i_18 0.85 0.94 1.09 1.08 1.4 71.581.751.721.471.581.751.72 ns diff_hstl_i_dci_18 0.85 0.94 1.09 1.08 1 .42 1.53 1.68 1.66 1.42 1.53 1.68 1.66 ns ta bl e 4 4 : iob switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1 -1l -3 -2 -1 -1l -3 -2 -1 -1l
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 29 diff_hstl_i 0.85 0.94 1. 09 1.08 1.45 1.56 1.73 1. 71 1.45 1.56 1.73 1.71 ns diff_hstl_i_dci 0.85 0.94 1.09 1.08 1.40 1.50 1.66 1. 64 1.40 1.50 1.66 1.64 ns diff_hstl_ii_18 0.85 0.94 1.09 1.08 1.50 1.62 1.81 1. 78 1.50 1.62 1.81 1.78 ns diff_hstl_ii_dci_18 0.85 0.94 1.09 1.08 1 .36 1.46 1.62 1.59 1.36 1.46 1.62 1.59 ns diff_hstl_ii _t_dci_18 0.85 0.94 1.09 1.0 81.421.531.681.661.421.531.681.66 ns diff_hstl_ii 0.85 0.94 1.09 1.08 1.44 1 .56 1.74 1.72 1.44 1.56 1.74 1.72 ns diff_hstl_ii_dci 0.85 0.94 1.09 1.08 1.37 1.49 1.68 1. 66 1.37 1.49 1.68 1.66 ns sstl2_i_dci 0.81 0.91 1. 06 1.06 1.42 1.53 1.70 1. 68 1.42 1.53 1.70 1.68 ns sstl2_ii_dci 0.81 0.91 1.06 1.06 1.39 1.50 1.67 1.69 1.39 1.50 1.67 1.69 ns sstl2_ii_t_dci 0.81 0.91 1.06 1.06 1.42 1.53 1.70 1.68 1.42 1.53 1.70 1.68 ns sstl18_i 0.81 0.91 1.06 1.06 1.47 1.5 81.751.731.471.581.751.73 ns sstl18_ii 0.81 0.91 1.06 1.06 1.39 1. 50 1.67 1.66 1.39 1.50 1.67 1.66 ns sstl18_i_dci 0.81 0.91 1.06 1.06 1.40 1.51 1.67 1.65 1.40 1.51 1.67 1.65 ns sstl18_ii_dci 0.81 0.91 1. 06 1.06 1.36 1.47 1.63 1. 62 1.36 1.47 1.63 1.62 ns sstl18_ii_t_dci 0.81 0.91 1.06 1.06 1.40 1.51 1.67 1. 65 1.40 1.51 1.67 1.65 ns sstl15_t_dci 0.81 0.91 1.06 1.06 1.41 1 .52 1.68 1.66 1.41 1.52 1.68 1.66 ns sstl15_dci 0.81 0.91 1.06 1.06 1.41 1. 52 1.68 1.66 1.41 1.52 1.68 1.66 ns diff_sstl2_i 0.85 0.94 1. 09 1.08 1.49 1.60 1.77 1. 74 1.49 1.60 1.77 1.74 ns diff_sstl2_i_dci 0. 85 0.94 1.09 1.08 1.42 1.53 1. 70 1.68 1.42 1.53 1.70 1.68 ns diff_sstl2_ii 0.85 0.94 1.09 1.08 1.42 1 .54 1.72 1.71 1.42 1.54 1.72 1.71 ns diff_sstl2_ii_dci 0.85 0.94 1.09 1.08 1.39 1.50 1.67 1. 69 1.39 1.50 1.67 1.69 ns diff_sstl2_ii_t_dci 0.85 0. 94 1.09 1.08 1.42 1.53 1.70 1.68 1.42 1.53 1.70 1.68 ns diff_sstl18_i 0.85 0.94 1.09 1.08 1.47 1 .58 1.75 1.73 1.47 1.58 1.75 1.73 ns diff_sstl18_i_dci 0.85 0.94 1.09 1.08 1.40 1.51 1.67 1. 65 1.40 1.51 1.67 1.65 ns diff_sstl18_ii 0.85 0.94 1. 09 1.08 1.39 1.50 1.67 1. 66 1.39 1.50 1.67 1.66 ns diff_sstl18_ii_dci 0.85 0. 94 1.09 1.08 1.36 1.47 1.63 1.62 1.36 1.47 1.63 1.62 ns diff_sstl18_ii_t_dci 0.85 0.94 1.09 1.08 1. 40 1.51 1.67 1.65 1. 40 1.51 1.67 1.65 ns diff_sstl15 0.81 0.91 1. 06 1.06 1.42 1.54 1.71 1. 69 1.42 1.54 1.71 1.69 ns diff_sstl15_dci 0.81 0.91 1. 06 1.06 1.41 1.52 1.68 1. 66 1.41 1.52 1.68 1.66 ns diff_sstl15_t_dci 0.81 0.91 1.06 1.06 1.41 1.52 1.68 1. 66 1.41 1.52 1.68 1.66 ns ta bl e 4 5 : iob 3-state on output switching characteristics (t iotphz ) symbol description speed grade units -3 -2 -1 -1l t iotphz t input to pad high-impedance 0.86 0.92 0.99 0.99 ns ta bl e 4 4 : iob switching characteristics (cont?d) i/o standard t iopi t ioop t iotp units speed grade speed grade speed grade -3 -2 -1 -1l -3 -2 -1 -1l -3 -2 -1 -1l
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 30 i/o standard adjustment measurement methodology input delay measurements ta bl e 4 6 shows the test setup parameters used for measuring input delay. ta bl e 4 6 : input delay measurement methodology description i /o standard attribute v l (1)(2) v h (1)(2) v meas (1)(4)(5) v ref (1)(3)(5) lvcmos, 2.5v lvcmos25 0 2.5 1.25 ? lvcmos, 1.8v lvcmos18 0 1.8 0.9 ? lvcmos, 1.5v lvcmos15 0 1.5 0.75 ? hstl (high-speed transceiver logic), class i & ii hstl_i, hstl_ii v ref ?0.5 v ref +0.5 v ref 0.75 hstl, class iii hstl_iii v ref ?0.5 v ref +0.5 v ref 0.90 hstl, class i & ii, 1.8v hstl_i_18, hstl_ii_18 v ref ?0.5 v ref +0.5 v ref 0.90 hstl, class iii 1.8v hstl_iii_18 v ref ?0.5 v ref +0.5 v ref 1.08 sstl (stub terminated transceiver logic), class i & ii, 3.3v sstl3_i, sstl3_ii v ref ?1.00 v ref +1.00 v ref 1.5 sstl, class i & ii, 2. 5v sstl2_i, sstl2_ii v ref ?0.75 v ref +0.75 v ref 1.25 sstl, class i & ii, 1.8v sstl18_i, sstl18_ii v ref ?0.5 v ref +0.5 v ref 0.90 lvds (low-voltage differential signal ing), 2.5v lvds_25 1.2 ? 0.125 1.2 + 0.125 0 (6) ? lvdsext (lvds extended mode), 2. 5v lvdsext_25 1.2 ? 0.125 1.2 + 0.125 0 (6) ? ht (hypertransport), 2.5v ldt_25 0.6 ? 0.125 0.6 + 0.125 0 (6) ? notes: 1. the input delay measurement methodology parameters for lvdci are the same for lvcmos standards of the same voltage. input del ay measurement methodology parameters for hslvdci are the same as for hstl_ii standards of the same voltage. parameters for all ot her dci standards are the same for the corresponding non-dci standards. 2. input waveform switches between v l and v h . 3. measurements are made at typical, minimum, and maximum v ref values. reported delays reflect worst case of these measurements. v ref values listed are typical. 4. input voltage level from which measurement starts. 5. this is an input voltage reference that bears no relation to the v ref / v meas parameters found in ibis models and/or noted in figure 6 . 6. the value given is the differential input voltage.
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 31 output delay measurements output delays are measured using a tektronix p6245 tds500/600 probe (< 1 pf) across approximately 4" of fr4 microstrip trace. standard termination was used for all testing. the propagation delay of the 4" trace is characterized separately and subtracted from the final measurement, and is therefore not included in the generalized test setups shown in figure 6 and figure 7 . measurements and test conditions are reflected in the ibis models except where the ibis format precludes it. parameters v ref , r ref , c ref , and v meas fully describe the test conditions for each i/o standard. the most accurate prediction of propagation delay in any given application can be obtained through ibis simulation, using the following method: 1. simulate the output driver of choice into the generalized test setup, using values from ta b l e 4 7 . 2. record the time to v meas . 3. simulate the output driver of choice into the actual pcb trace and load, using the appropriate ibis model or capacitance value to represent the load. 4. record the time to v meas . 5. compare the results of steps 2 and 4. the increase or decrease in delay yields the actual propagation delay of the pcb trace. x-ref target - figure 6 figure 6: single ended test setup v ref r ref v mea s (volt a ge level when t a king del a y me asu rement) c ref (pro b e c a p a cit a nce) fpga o u tp u t d s 152_06_042109 x-ref target - figure 7 figure 7: differential test setup r ref v mea s + ? c ref fpga o u tp u t d s 152_07_042109 ta bl e 4 7 : output delay measurement methodology description i/o standard attribute r ref ( ? ) c ref (1) (pf) v meas (v) v ref (v) lvcmos, 2.5v lvcmos25 1m 0 1.25 0 lvcmos, 1.8v lvcmos18 1m 0 0.9 0 lvcmos, 1.5v lvcmos15 1m 0 0.75 0 lvcmos, 1.2v lvcmos12 1m 0 0.75 0 hstl (high-speed transceiver logic), class i hstl_i 50 0 v ref 0.75 hstl, class ii hstl_ii 25 0 v ref 0.75 hstl, class iii hstl_iii 50 0 0.9 1.5 hstl, class i, 1.8v hstl_i_18 50 0 v ref 0.9 hstl, class ii, 1.8v hstl_ii_18 25 0 v ref 0.9 hstl, class iii, 1.8v hstl_iii_18 50 0 1.1 1.8 sstl (stub series terminated logic), class i, 1.8v sstl18_i 50 0 v ref 0.9 sstl, class ii, 1.8v sstl18_ii 25 0 v ref 0.9 sstl, class i, 2.5v sstl2_i 50 0 v ref 1.25 sstl, class ii, 2.5v sstl2_ii 25 0 v ref 1.25 lvds (low-voltage differential signaling), 2.5v lvds_25 100 0 0 (2) 1.2 lvdsext (lvds extended mode), 2.5v lvds_25 100 0 0 (2) 1.2 blvds (bus lvds), 2.5v blvds_25 100 0 0 (2) 0
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 32 input/output logic switching characteristics ht (hypertransport), 2.5v ldt_25 100 0 0 (2) 0.6 lvpecl (low-voltage positi ve emitter-coupled logic), 2.5v lvpecl_25 100 0 0 (2) 0 lvdci/hslvdci, 2.5v lvdci_25, hslvdci_25 1m 0 1.25 0 lvdci/hslvdci, 1.8v lvdci_18, hslvdci_18 1m 0 0.9 0 lvdci/hslvdci, 1.5v lvdci_15, hslvdci_15 1m 0 0.75 0 hstl (high-speed transceiver logic), class i & ii, with dci hstl_i_dci, hstl_ii_dci 50 0 v ref 0.75 hstl, class iii, with dci hstl_iii_dci 50 0 0.9 1.5 hstl, class i & ii, 1.8v, with dci hstl_i_dci_18, hstl_ii_dci_18 50 0 v ref 0.9 hstl, class iii, 1.8v, with dci hstl_iii_dci_18 50 0 1.1 1.8 sstl (stub series termi.logic), class i & ii, 1.8v, with dci sstl18_i_dci, sstl18_ii_dci 50 0 v ref 0.9 sstl, class i & ii, 2.5v, with dci sstl2_i_dci, sstl2_ii_dci 50 0 v ref 1.25 notes: 1. c ref is the capacitance of the probe, nominally 0 pf. 2. the value given is the differential output voltage. ta bl e 4 8 : ilogic switching characteristics symbol description speed grade units -3 -2 -1 -1l setup/hold t ice1ck /t ickce1 ce1 pin setup/hold with respect to clk 0.21/ 0.03 0.25/ 0.04 0.27/ 0.04 0.31/ 0.05 ns t isrck /t icksr sr pin setup/hold with respect to clk 0.66/ ?0.08 0.78/ ?0.08 0.96/ ?0.08 1.09/ ?0.11 ns t idock /t iockd d pin setup/hold with respect to clk without delay 0.07/ 0.41 0.08/ 0.46 0.10/ 0.54 0.11/ 0.64 ns t idockd /t iockdd ddly pin setup/hold with respect to clk (using iodelay) 0.10/ 0.32 0.12/ 0.36 0.14/ 0.42 0.16/ 0.50 ns combinatorial t idi d pin to o pin propagation delay, no delay 0.15 0.17 0.20 0.23 ns t idid ddly pin to o pin propagation delay (using iodelay) 0.19 0.22 0.25 0.28 ns sequential delays t idlo d pin to q1 pin using flip-flop as a latch without delay 0.48 0.54 0.64 0.73 ns t idlod ddly pin to q1 pin using flip-flop as a latch (using iodela y) 0.52 0.58 0.68 0.78 ns t ickq clk to q outputs 0. 54 0.61 0.70 0.93 ns t rq_ilogic sr pin to oq/tq ou t 0.85 0.97 1.15 1.32 ns t gsrq_ilogic global set/reset to q outputs 7.60 7.60 10.51 10.51 ns set/reset t rpw_ilogic minimum pulse width, sr in puts 0.78 0.95 1.20 1.30 ns, min ta bl e 4 7 : output delay measurement methodology (cont?d) description i/o standard attribute r ref ( ? ) c ref (1) (pf) v meas (v) v ref (v)
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 33 ta bl e 4 9 : ologic switching characteristics symbol description speed grade units -3 -2 -1 -1l setup/hold t odck /t ockd d1/d2 pins setup/hold with respect to clk 0.45/ ?0.08 0.50/ ?0.08 0.54/ ?0.08 0.69/ ?0.11 ns t ooceck /t ockoce oce pin setup/hold with respect to clk 0.17/ ?0.03 0.20/ ?0.03 0.22/ ?0.03 0.27/ ?0.04 ns t osrck /t ocksr sr pin setup/hold with respect to clk 0.59/ ?0.24 0.62/ ?0.24 0.71/ ?0.24 0.79/ ?0.35 ns t otck /t ockt t1/t2 pins setup/hold with respect to clk 0.44/ ?0.07 0.51/ ?0.07 0.56/ ?0.07 0.68/ ?0.13 ns t otceck /t ocktce tce pin setup/hold with respect to clk 0.15/ ?0.04 0.19/ ?0.04 0.21/ ?0.04 0.29/ ?0.05 ns combinatorial t doq d1 to oq out or t1 to tq out 0.78 0.87 1.01 1.15 ns sequential delays t ockq clk to oq/tq out 0.54 0.61 0.71 0.80 ns t rq sr pin to oq/tq out 0.80 0.90 1.05 1.19 ns t gsrq global set/reset to q outputs 7.60 7.60 10.51 10.51 ns set/reset t rpw minimum pulse width, sr inputs 0.78 0.95 1.20 1.30 ns, min
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 34 input serializer/deserializer switching characteristics ta bl e 5 0 : iserdes switching characteristics symbol description speed grade units -3 -2 -1 -1l setup/hold for control lines t iscck_bitslip / t isckc_bitslip bitslip pin setup/hold with respect to clkdiv 0.07/ 0.15 0.08/ 0.16 0.09/ 0.17 0.14/ 0.17 ns t iscck_ce / t isckc_ce (2) ce pin setup/hold with respect to clk (for ce1) 0.20/ 0.03 0.25/ 0.04 0.27/ 0.04 0.31/ 0.05 ns t iscck_ce2 / t isckc_ce2 (2) ce pin setup/hold with respect to clkdiv (for ce2) 0.01/ 0.27 0.01 0.29 0.01/ 0.31 ?0.05/ 0.35 ns setup/hold for data lines t isdck_d /t isckd_d d pin setup/hold with respect to clk 0.07/ 0.08 0.08/ 0.09 0.09/ 0.11 0.11/ 0.19 ns t isdck_ddly /t isckd_ddly ddly pin setup/hold with respect to clk (using iodelay) (1) 0.10/ 0.05 0.12/ 0.06 0.14/ 0.07 0.16/ 0.15 ns t isdck_d_ddr /t isckd_d_ddr d pin setup/hold with respect to clk at ddr mode 0.07/ 0.08 0.08/ 0.09 0.09/ 0.11 0.11/ 0.19 ns t isdck_ddly_ddr t isckd_ddly_ddr d pin setup/hold with respect to clk at ddr mode (using iodelay) (1) 0.10/ 0.05 0.12/ 0.06 0.14/ 0.07 0.16/ 0.15 ns sequential delays t iscko_q clkdiv to out at q pin 0.57 0.66 0.75 0.88 ns propagation delays t isdo_do d input to do output pin 0.19 0.22 0.25 0.28 ns notes: 1. recorded at 0 tap value. 2. t iscck_ce2 and t isckc_ce2 are reported as t iscck_ce /t isckc_ce in trace report.
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 35 output serializer/deserializ er switching characteristics ta bl e 5 1 : oserdes switching characteristics symbol description speed grade units -3 -2 -1 -1l setup/hold t osdck_d /t osckd_d d input setup/hold with respect to clkdiv 0.23/ ?0.10 0.28/ ?0.10 0.31/ ?0.10 0.36/ ?0.15 ns t osdck_t /t osckd_t (1) t input setup/hold with respect to clk 0.44/ ?0.10 0.51/ ?0.09 0.56/ ?0.08 0.68/ ?0.15 ns t osdck_t2 /t osckd_t2 (1) t input setup/hold with respect to clkdiv 0.25/ ?0.10 0.27/ ?0.09 0.31/ ?0.08 0.47/ ?0.15 ns t oscck_oce /t osckc_oce oce input setup/hold with respect to clk 0.17/ ?0.03 0.20/ ?0.03 0.22/ ?0.03 0.27/ ?0.04 ns t oscck_s sr (reset) input setup with resp ect to clkdiv 0.07 0.07 0.07 0.08 ns t oscck_tce /t osckc_tce tce input setup/hold with respect to clk 0.15/ ?0.04 0.19/ ?0.04 0.21/ ?0.04 0.29/ ?0.05 ns sequential delays t oscko_oq clock to out from clk to oq 0.63 0.71 0.82 0.93 ns t oscko_tq clock to out from clk to tq 0.63 0.71 0.82 0.93 ns combinatorial t osdo_ttq t input to tq out 0.76 0.84 0.97 1.11 ns notes: 1. t osdck_t2 and t osckd_t2 are reported as t osdck_t /t osckd_t in trace report.
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 36 input/output delay swit ching characteristics ta bl e 5 2 : input/output delay switching characteristics symbol description speed grade units -3 -2 -1 -1l idelayctrl t dlycco_rdy reset to ready for idelayctrl 3.00 3.00 3.00 3.25 s f idelayctrl_ref attribute refclk frequency = 200.0 (1) 200 200 200 200 mhz attribute refclk frequency = 300.0 (1) 300 300 ? ? mhz idelayctrl_ref_precision refclk precision 10 10 10 10 mhz t idelayctrl_rpw minimum reset pulse width 50.00 50.00 50.00 52.50 ns iodelay t idelayresolution iodelay chain delay resolution 1/(32 x 2 x f ref )ps t idelaypat_jit pattern dependent period jitter in delay chain for clock pattern. (2) 0000ps per tap pattern dependent period jitter in delay chain for random data pattern (prbs 23). (3) 5 5 5 5 ps per tap pattern dependent period jitter in delay chain for random data pattern (prbs 23). (4) 9 9 9 9 ps per tap t iodelay_clk_max maximum frequency of clk input to iodelay 500.00 420.00 300.00 300.00 mhz t iodcck_ce / t iodckc_ce ce pin setup/hold with respect to ck 0.45/ ?0.09 0.53/ ?0.09 0.65/ ?0.09 0.84/ ?0.14 ns t iodck_inc / t iodckc_inc inc pin setup/hold with respect to ck 0.23/ ?0.02 0.27/ ?0.01 0.31/ 0.00 0.27/ ?0.04 ns t iodcck_rst / t iodckc_rst rst pin setup/hold with respect to ck 0.57/ ?0.08 0.62/ ?0.08 0.69/ ?0.08 0.74/ ?0.13 ns t ioddo_t tscontrol delay to muxe/muxf switching and through iodelay note 5 note 5 note 5 note 5 ps t ioddo_idatain propagation delay through iodelay note 5 note 5 note 5 note 5 ps t ioddo_odatain propagation delay through iodelay note 5 note 5 note 5 note 5 ps notes: 1. average tap delay at 200 mhz = 78 ps, at 300 mhz = 52 ps. 2. when high_performance mode is set to true or false. 3. when high_performance mode is set to true 4. when high_performance mode is set to false. 5. delay depends on iodelay tap setting. see trace report for actual values.
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 37 clb switching characteristics ta bl e 5 3 : clb switching characteristics symbol description speed grade units -3 -2 -1 -1l combinatorial delays t ilo an ? dn lut address to a 0.06 0.07 0.07 0.09 ns, max an ? dn lut address to amux/cmux 0.18 0.20 0.22 0.25 ns, max an ? dn lut address to bmux_a 0.28 0.31 0.36 0.40 ns, max t ito an ? dn inputs to a ? d q outputs 0.59 0.67 0.79 0.85 ns, max t axa ax inputs to amux output 0.31 0.35 0.42 0.44 ns, max t axb ax inputs to bmux output 0.35 0.39 0.47 0.50 ns, max t axc ax inputs to cmux output 0.39 0.44 0.52 0.56 ns, max t axd ax inputs to dmux output 0.42 0.47 0.55 0.60 ns, max t bxb bx inputs to bmux output 0.30 0.34 0.39 0.44 ns, max t bxd bx inputs to dmux output 0.38 0.43 0.50 0.55 ns, max t cxc cx inputs to cmux output 0.26 0.29 0.34 0.37 ns, max t cxd cx inputs to dmux output 0.30 0.34 0.40 0.44 ns, max t dxd dx inputs to dmux output 0.30 0.33 0.38 0.43 ns, max t opcya an input to cout output 0.32 0.36 0.41 0.47 ns, max t opcyb bn input to cout output 0.32 0.36 0.41 0.47 ns, max t opcyc cn input to cout output 0.27 0.30 0.34 0.40 ns, max t opcyd dn input to cout output 0.25 0.28 0.32 0.37 ns, max t axcy ax input to cout output 0.25 0.28 0.33 0.36 ns, max t bxcy bx input to cout output 0.22 0.24 0.28 0.31 ns, max t cxcy cx input to cout output 0.15 0.17 0.20 0.22 ns, max t dxcy dx input to cout output 0.14 0.16 0.19 0.21 ns, max t byp cin input to cout output 0.06 0.07 0.08 0.09 ns, max t cina cin input to amux output 0.21 0.24 0.28 0.30 ns, max t cinb cin input to bmux output 0.23 0.25 0.29 0.31 ns, max t cinc cin input to cmux output 0.23 0.26 0.30 0.33 ns, max t cind cin input to dmux output 0.25 0.29 0.33 0.36 ns, max sequential delays t cko clock to aq ? dq outputs 0.29 0.33 0.39 0.44 ns, max t shcko clock to amux ? dmux outputs 0.36 0.40 0.47 0.53 ns, max setup and hold times of clb fl ip-flops before/after clock clk t dick /t ckdi a ? d input to clk on a ? d flip flops 0.30/ 0.17 0.36/ 0.18 0.43/ 0.20 0.44/ 0.25 ns, min t ceck_clb / t ckce_clb ce input to clk on a ? d flip flops 0.20/ 0.00 0.25/ 0.00 0.32/ 0.00 0.32/ 0.01 ns, min t srck /t cksr sr input to clk on a ? d flip flops 0.39/ ?0.07 0.44/ ?0.07 0.52/ ?0.07 0.58/ ?0.08 ns, min t cinck /t ckcin cin input to clk on a ? d flip flops 0.16/ 0.12 0.19/ 0.14 0.24/ 0.16 0.23/ 0.22 ns, min
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 38 clb distributed ram switching characteristics (slicem only) set/reset t srmin sr input minimum pulse width 0.90 0.90 0.97 0.80 ns, min t rq delay from sr input to aq ? dq flip-flops 0.52 0.58 0.68 0.77 ns, max t ceo delay from ce input to aq ? dq flip-flops 0.41 0.48 0.59 0.61 ns, max f tog toggle frequency (for export cont rol) 1412.00 1286.40 1098.00 1098.00 mhz notes: 1. a zero ?0? hold time listing indicates no hold ti me or a negative hold time. negative values can not be guaranteed ?best-case?, but if a ?0? is listed, there is no positive hold time. 2. these items are of interest for carry chain applications. ta bl e 5 4 : clb distributed ram swit ching characteristics symbol description speed grade units -3 -2 -1 -1l sequential delays t shcko clock to a ? b outputs 0.92 1.10 1.36 1.49 ns, max t shcko_1 clock to amux ? bmux outputs 1.19 1.40 1.71 1.87 ns, max setup and hold times before/after clock clk t ds /t dh a ? d inputs to clk 0.62/ 0.18 0.72/ 0.20 0.88/ 0.22 0.98/ 0.23 ns, min t as /t ah address an inputs to clock 0.19/ 0.52 0.22/ 0.59 0.27/ 0.66 0.30/ 0.75 ns, min t ws /t wh we input to clock 0.27/ 0.00 0.32/ 0.00 0.40/ 0.00 0.47/ ?0.03 ns, min t ceck /t ckce ce input to clk 0.28/ ?0.01 0.34/ ?0.01 0.41/ ?0.01 0.48/ ?0.05 ns, min clock clk t mpw minimum pulse width 0.70 0.82 1.00 1.04 ns, min t mcp minimum clock period 1.40 1.64 2.00 2.08 ns, min notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case? , but if a ?0? is listed, there is no positive hold time. 2. t shcko also represents the clk to xmux output. refer to trace report for the clk to xmux path. ta bl e 5 3 : clb switching characteristics (cont?d) symbol description speed grade units -3 -2 -1 -1l
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 39 clb shift register switching characteristics (slicem only) ta bl e 5 5 : clb shift register switching characteristics symbol description speed grade units -3 -2 -1 -1l sequential delays t reg clock to a ? d outputs 1.11 1.30 1.58 1.74 ns, max t reg_mux clock to amux ? dmux output 1.37 1.60 1.93 2.12 ns, max t reg_m31 clock to dmux output via m31 output 1.08 1.27 1.55 1.74 ns, max setup and hold times before/after clock clk t ws /t wh we input 0.05/ 0.00 0.07/ 0.00 0.09/ 0.00 0.11/ 0.03 ns, min t ceck /t ckce ce input to clk 0.06/ ?0.01 0.08/ ?0.01 0.10/ ?0.01 0.12/ 0.02 ns, min t ds /t dh a ? d inputs to clk 0.64/ 0.18 0.76/ 0.21 0.94/ 0.24 1.07/ 0.23 ns, min clock clk t mpw minimum pulse width 0.60 0.70 0.85 0.89 ns, min notes: 1. a zero ?0? hold time listing indicates no hold time or a negative hold time. negative values cannot be guaranteed ?best-case? , but if a ?0? is listed, there is no positive hold time.
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 40 block ram and fifo switching characteristics ta bl e 5 6 : block ram and fifo switching characteristics symbol description speed grade units -3 -2 -1 -1l block ram and fifo clock-to-out delays t rcko_do and t rcko_do_reg (1) clock clk to dout out put (without output register) (2)(3) 1.60 1.79 2.08 2.36 ns, max clock clk to dout output (with output register) (4)(5) 0.60 0.66 0.75 0.83 ns, max t rcko_do_ecc and t rcko_do_ecc_reg clock clk to dout output with ecc (without outpu t register) (2)(3) 2.62 2.89 3.30 3.73 ns, max clock clk to dout output with ecc (with output register) (4)(5) 0.71 0.77 0.86 0.94 ns, max t rcko_casc and t rcko_casc_reg clock clk to dout output with cascade (without outpu t register) (2) 2.49 2.77 3.18 3.61 ns, max clock clk to dout output with cascade (with output register) (4) 1.29 1.41 1.58 1.79 ns, max t rcko_flags clock clk to fifo flags outputs (6) 0.74 0.81 0.91 0.98 ns, max t rcko_pointers clock clk to fifo pointers outputs (7) 0.90 0.98 1.09 1.21 ns, max t rcko_sdbit_ecc and t rcko_sdbit_ecc_reg clock clk to biterr (with output register) 0.62 0.68 0.76 0.82 ns, max clock clk to biterr (without output register) 2.21 2.46 2.84 3.23 ns, max t rcko_parity_ecc clock clk to eccparity in ecc encode only mode 0.86 0.94 1.06 1.18 ns, max t rcko_rdaddr_ecc and t rcko_rdaddr_ecc_reg clock clk to rdaddr output with ecc (without outpu t register) 0.73 0.79 0.90 1.00 ns, max clock clk to rdaddr output with ecc (with output register) 0.76 0.82 0.92 1.02 ns, max setup and hold times before/after clock clk t rcck_addr /t rckc_addr addr inputs (8) 0.47/ 0.27 0.53/ 0.29 0.62/ 0.32 0.66/ 0.34 ns, min t rdck_di /t rckd_di din inputs (9) 0.84/ 0.30 0.95/ 0.32 1.11/ 0.34 1.26/ 0.36 ns, min t rdck_di_ecc /t rckd_di_ecc din inputs with block ram ecc in standard mode (9) 0.47/ 0.30 0.52/ 0.32 0.59/ 0.34 0.68/ 0.36 ns, min din inputs with block ram ecc encode only (9) 0.68/ 0.30 0.75/ 0.32 0.85/ 0.34 0.97/ 0.36 ns, min din inputs with fifo ecc in standard mode (9) 0.77/ 0.30 0.87/ 0.32 1.02/ 0.34 1.16/ 0.36 ns, min t rcck_clk /t rckc_clk inject single/double bit error in ecc mode 0.90/ 0.27 1.02/ 0.28 1.20/ 0.29 1.56/ 0.29 ns, min t rcck_rden /t rckc_rden block ram enable (en) input 0.31/ 0.26 0.35/ 0.27 0.41/ 0.30 0.44/ 0.31 ns, min t rcck_regce /t rckc_regce ce input of out put register 0.18/ 0.25 0.19/ 0.27 0.22/ 0.31 0.24/ 0.33 ns, min t rcck_rstreg /t rckc_rstreg synchronous rstreg input 0.22/ 0.23 0.24/ 0.24 0.28/ 0.26 0.31/ 0.27 ns, min t rcck_rstram /t rckc_rstram synchronous rstram input 0.32/ 0.23 0.36/ 0.24 0.41/ 0.27 0.46/ 0.29 ns, min
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 41 dsp48e1 switching characteristics t rcck_we /t rckc_we write enable (we) input (block ram only) 0.44/ 0.19 0.47/ 0.25 0.52/ 0.35 0.67/ 0.24 ns, min t rcck_wren /t rckc_wren wren fifo inputs 0.47/ 0.26 0.50/ 0.27 0.55/ 0.30 0.68/ 0.31 ns, min t rcck_rden /t rckc_rden rden fifo inputs 0.46/ 0.26 0.50/ 0.27 0.55/ 0.30 0.67/ 0.31 ns, min reset delays t rco_flags reset rst to fifo flags/pointers (10) 0.90 0.98 1.10 1.23 ns, max t rcck_rstreg /t rckc_rstreg fifo reset timing (11) 0.22/ 0.23 0.24/ 0.24 0.28/ 0.26 0.31/ 0.27 ns, min maximum frequency f max block ram in tdp and sdp modes (write first and no change modes) 600 540 450 340 mhz block ram (read first mode) 525 475 400 275 mhz block ram (sdp mode) (12) 525 475 400 275 mhz f max_cascade block ram cascade (write first and no change modes) 550 490 400 300 mhz block ram cascade (read first mode) 475 425 350 235 mhz f max_fifo fifo in all modes 600 540 450 340 mhz f max_ecc block ram and fifo in ecc configuration 450 400 325 250 mhz notes: 1. trace will report all of these parameters as t rcko_do . 2. t rcko_dor includes t rcko_dow , t rcko_dopr , and t rcko_dopw as well as the b port equivalent timing parameters. 3. these parameters also apply to synchronous fifo with do_reg = 0. 4. t rcko_do includes t rcko_dop as well as the b port equivalent timing parameters. 5. these parameters also apply to multirate (asynchronous) and synchronous fifo with do_reg = 1. 6. t rcko_flags includes the following parameters: t rcko_aempty , t rcko_afull , t rcko_empty , t rcko_full , t rcko_rderr , t rcko_wrerr. 7. t rcko_pointers includes both t rcko_rdcount and t rcko_wrcount. 8. the addr setup and hold must be met when en is asserted (even when we is deasserted) . otherwise, block ram data corruption is possible. 9. t rcko_di includes both a and b inputs as well as the parity inputs of a and b. 10. t rco_flags includes the following flags: aempty, afull, em pty, full, rderr, wrerr, rdcount, and wrcount. 11. the fifo reset must be asserted for at least three positive clock edges. 12. when using ise software v12.4 or later, if the rdarrdr_colli sion_hwconfig attribute is set to performance or the block ram is in single-port operation, then the faster f max for write_first/no_change modes apply. ta bl e 5 7 : dsp48e1 switching characteristics symbol description speed units -3 -2 -1 -1l setup and hold times of data/control pins to the input register clock t dspdck_{a, acin; b, bcin}_{areg; breg} / t dspckd_{a, acin; b, bcin}_{areg; breg} {a, acin, b, bcin} input to {a, b} register clk 0.25/ 0.27 0.29/ 0.30 0.35/ 0.34 0.46/ 0.39 ns t dspdck_c_creg /t dspckd_c_creg c input to c register clk 0.16/ 0.20 0.19/ 0.22 0.22/ 0.24 0.33/ 0.30 ns t dspdck_d_dreg /t dspckd_d_dreg d input to d register clk 0.07/ 0.31 0.10/ 0.34 0.15/ 0.39 0.24/ 0.45 ns ta bl e 5 6 : block ram and fifo switching characteristics (cont?d) symbol description speed grade units -3 -2 -1 -1l
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 42 setup and hold times of data pins to the pipeline register clock t dspdck_{a, acin, b, bcin}_mreg_mult / t dspckd_{a, acin, b, bcin}_mreg_mult {a, acin, b, bcin} input to m register clk 2.36/ 0.04 2.70/ 0.04 3.21/ 0.04 3.66/ 0.02 ns t dspdck_{a, d}_adreg / t dspckd_{a, d}_adreg {a, d} input to ad register clk 1.24/ 0.10 1.42/ 0.12 1.69/ 0.13 1.91/ 0.16 ns setup and hold times of data/control pins to the output register clock t dspdck_{a, acin, b, bcin}_preg_mult / t dspckd_{a, acin, b, bcin}_preg_mult {a, acin, b, bcin} input to p register clk using multiplier 3.83/ ?0.13 4.37/ ?0.13 5.20/ ?0.13 5.94/ ?0.24 ns t dspdck_d_preg_mult / t dspckd_d_preg_mult d input to p register clk 3.62/ ?0.47 4.13/ ?0.47 4.90/ ?0.47 5.61/ ?0.77 ns t dspdck_{a, acin, b, bcin}_preg / t dspckd_{a, acin, b, bcin}_preg {a, acin, b, bcin} input to p register clk not using multiplier 1.59/ ?0.13 1.81/ ?0.13 2.15/ ?0.13 2.44/ ?0.24 ns t dspdck_c_preg / t dspckd_c_preg c input to p register clk 1.42/ ?0.10 1.61/ ?0.10 1.91/ ?0.10 2.16/ ?0.19 ns t dspdck_{pcin, carrycascin, multsignin}_preg / t dspckd_{pcin, carrycasc in, multsignin}_preg {pcin, carrycascin, multsignin} input to p register clk 1.23/ ?0.02 1.41/ ?0.02 1.67/ ?0.02 1.91/ ?0.07 ns setup and hold times of the ce pins t dspdck_{cea; ceb}_{areg; breg} / t dspckd_{cea; ceb}_{areg; breg} {cea; ceb} input to {a; b} register clk 0.14/ 0.19 0.17/ 0.22 0.22/ 0.25 0.30/ 0.28 ns t dspdck_cec_creg / t dspckd_cec_creg cec input to c register clk 0.15/ 0.18 0.18/ 0.20 0.24/ 0.23 0.31/ 0.26 ns t dspdck_ced_dreg / t dspckd_ced_dreg ced input to d register clk 0.20/ 0.12 0.24/ 0.13 0.31/ 0.14 0.43/ 0.16 ns t dspdck_cem_mreg / t dspckd_cem_mreg cem input to m register clk 0.16/ 0.19 0.20/ 0.21 0.26/ 0.25 0.32/ 0.28 ns t dspdck_cep_preg / t dspckd_cep_preg cep input to p register clk 0.32/ 0.02 0.38/ 0.02 0.46/ 0.03 0.54/ 0.04 ns setup and hold times of the rst pins t dspdck_{rsta; rstb}_{areg; breg} / t dspckd_{rsta; rstb}_{areg; breg} {rsta, rstb} input to {a, b} register clk 0.27/ 0.17 0.31/ 0.19 0.38/ 0.22 0.41/ 0.25 ns t dspdck_rstc_creg / t dspckd_rstc_creg rstc input to c register clk 0.18/ 0.08 0.20/ 0.08 0.23/ 0.09 0.27/ 0.11 ns t dspdck_rstd_dreg / t dspckd_rstd_dreg rstd input to d register clk 0.28/ 0.15 0.32/ 0.16 0.38/ 0.19 0.45/ 0.21 ns t dspdck_rstm_mreg / t dspckd_rstm_mreg rstm input to m register clk 0.20/ 0.24 0.23/ 0.26 0.26/ 0.30 0.29/ 0.34 ns t dspdck_rstp_preg / t dspckd_rstp_preg rstp input to p register clk 0.26/ 0.04 0.30/ 0.04 0.35/ 0.05 0.43/ 0.06 ns combinatorial delays from input pins to output pins t dspdo_{a, b}_{p, carryout}_mult {a, b} input to {p, carryout} output using multiplier 3.76 4.29 5.08 5.87 ns t dspdo_d_{p, carryout}_mult d input to {p, carryout} output using multiplier 3.57 4.07 4.82 5.57 ns t dspdo_{a, b}_{p, carryout} {a, b} input to {p, carryout} output not using multiplier 1.55 1.76 2.07 2.41 ns t dspdo_{c, carryin}_{p, carryout} {c, carryin} input to {p, carryout} output 1.38 1.56 1.83 2.13 ns ta bl e 5 7 : dsp48e1 switching characteristics (cont?d) symbol description speed units -3 -2 -1 -1l
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 43 combinatorial delays from input pins to cascading output pins t dspdo_{a; b}_{acout; bcout} {a, b} input to {acout, bc out} output 0.49 0.56 0.65 0.73 ns t dspdo_{a, b}_{pcout, carrycascout, multsignout}_mult {a, b} input to {pcout, carrycascout, multsignout} output using multiplier 3.87 4.42 5.24 6.09 ns t dspdo_d_{pcout, carrycascout, multsignout}_mult d input to {pcout, carrycascout, multsignout} output using multiplier 3.66 4.17 4.94 5.76 ns t dspdo_{a, b}_{pcout, carrycascout, multsignout} {a, b} input to {pcout, carrycascout, multsignout} output not using multiplier 1.64 1.86 2.19 2.60 ns t dspdo__{c, carryin}_{pcout, carrycascout,multsignout} {c, carryin} input to {pcout, carrycascout, multsignout} output 1.46 1.66 1.95 2.32 ns combinatorial delays from cascading input pins to all output pins t dspdo_{acin, bcin}_{p, carryout}_mult {acin, bcin} input to {p, carryout} output using multiplier 3.67 4.19 4.97 5.75 ns t dspdo_{acin, bcin}_{p, carryout {acin, bcin} input to {p, carryout} output not using multiplier 1.43 1.63 1.92 2.25 ns t dspdo_{acin; bcin}_{acout; bcout} {acin, bcin} input to {acout, bcout} output 0.36 0.42 0.49 0.56 ns t dspdo_{acin, bcin}_{p cout, carrycascout, multsignout}_mult {acin, bcin} input to {pcout, carrycascout, multsignout} output using multiplier 3.76 4.29 5.10 5.94 ns t dspdo_{acin, bcin}_{p cout, carrycascout, multsignout} {acin, bcin} input to {pcout, carrycascout, multsignout} output not using multiplier 1.52 1.73 2.05 2.44 ns t dspdo_{pcin, carrycascin, multsignin}_ {p, carryout} {pcin, carrycascin, multsignin} input to {p, carryout} output 1.19 1.35 1.60 1.87 ns t dspdo_{pcin, carrycascin , multsignin}_ {pcout, carrycascout, multsignout} {pcin, carrycascin, multsignin} input to {pcout, carrycascout, multsignout} output 1.28 1.46 1.72 2.06 ns clock to outs from output re gister clock to output pins t dspcko_{p, carryout}_preg clk (preg) to {p, carryout} output 0.38 0.43 0.50 0.57 ns t dspcko_{pcout, carrycascout, multsignout}_preg clk (preg) to {carrycascout, pcout, multsignout} output 0.50 0.56 0.66 0.76 ns clock to outs from pipeline register clock to output pins t dspcko_{p, carryout}_mreg clk (mreg) to {p, carryout} output 1.72 1.96 2.30 2.69 ns t dspcko_{pcout, carrycascout, multsignout}_mreg clk (mreg) to {pcout, carrycascout, multsignout} output 1.81 2.06 2.43 2.88 ns t dspcko_{p, carryout}_adreg_mult clk (adreg) to {p, carryout} output 2.79 3.16 3.72 4.32 ns t dspcko_{pcout, carrycascout, multsignout}_adreg_mult clk (adreg) to {pcout, carrycascout, multsignout} output 2.87 3.26 3.84 4.51 ns ta bl e 5 7 : dsp48e1 switching characteristics (cont?d) symbol description speed units -3 -2 -1 -1l
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 44 configuration switching characteristics clock to outs from input re gister clock to output pins t dspcko_{p, carryout }_{areg, breg}_mult clk (areg, breg) to {p, carryout} output using multiplier 3.97 4.52 5.36 6.20 ns t dspcko_{p, carryout}_{areg, breg} clk (areg, breg) to {p, carryout} output not using multiplier 1.70 1.93 2.27 2.65 ns t dspcko_{p, carryout}_creg clk (creg) to {p, carryo ut} output 1.70 1.93 2.27 2.80 ns t dspcko_{p, carryout}_dreg_mult clk (dreg) to {p, carryo ut} output 3.89 4.44 5.25 6.07 ns clock to outs from input register clock to cascadi ng output pins t dspcko_{acout; bcout}_{areg; breg} clk (areg, breg) to {p, carryout} output 0.66 0.76 0.89 1.01 ns t dspcko_{pcout, carrycascout, multsignout}_{areg, breg}_mult clk (areg, breg) to {pcout, carrycascout, multsignout} output using multiplier 4.05 4.63 5.49 6.39 ns t dspcko_{pcout, carrycascout, multsignout}_{areg, breg} clk (areg, breg) to {pcout, carrycascout, multsignout} output not using multiplier 1.79 2.03 2.40 2.84 ns t dspcko_{pcout, carrycascout, multsignout}_dreg_mult clk (dreg) to {pcout, carrycascout, multsignout} output using multiplier 3.98 4.54 5.38 6.26 ns t dspcko_{pcout, carrycascout, multsignout}_creg clk (creg) to {pcout, carrycascout, multsignout} output 1.78 2.03 2.40 2.99 ns maximum frequency f max with all registers used 600 540 450 410 mhz f max_patdet with pattern detector 551 483 408 356 mhz f max_mult_nomreg two register multiply without mreg 356 311 262 224 mhz f max_mult_nomreg_patdet two register multiply without mreg with pattern detect 327 286 241 211 mhz f max_preadd_mult_noadreg without adreg 398 347 292 254 mhz f max_preadd_mult_noadreg_patdet without adreg with pattern detect 398 347 292 254 mhz f max_nopipelinereg without pipeline registers (mreg, adreg) 266 233 196 171 mhz f max_nopipelinereg_patdet without pipeline registers (mreg, adreg) with pattern detect 250 219 184 160 mhz ta bl e 5 8 : configuration switching characteristics symbol description speed grade units -3 -2 -1 -1l power-up timing characteristics t pl (1) program latency 5 5 5 5 ms, max t por (1) power-on-reset 15/55 15/55 15/55 15/60 ms, min/max t icck cclk (output) delay 400 400 400 400 ns, min t program program pulse width 250 250 250 250 ns, min ta bl e 5 7 : dsp48e1 switching characteristics (cont?d) symbol description speed units -3 -2 -1 -1l
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 45 master/slave serial mode programming switching t dcck /t cckd din setup/hold, slave mode 4.0/0.0 4.0/0.0 4.0/0.0 4.5/0.0 ns, min t dscck /t scckd din setup/hold, master mode 4.0/0.0 4.0/0.0 4.0/0.0 5.0/0.0 ns, min t cco dout at 2.5v 6 6 6 7 ns, max dout at 1.8v 6 6 6 7 ns, max f mcck maximum cclk frequency, serial modes 100 100 100 70 mhz, max f mccktol frequency tolerance, master mode with respect to nominal cclk. 55 55 55 60 % f mscck slave mode external cclk 100 100 100 100 mhz selectmap mode programming switching t smdcck /t smcckd selectmap data setup/hold 4.0/0.0 4.0/0.0 4.0/0.0 5.5/0.0 ns, min t smcscck /t smcckcs csi_b setup/hold 4.0/0.0 4.0/0.0 4.0/0.0 5.5/0.0 ns, min t smcckw /t smwcck rdwr_b setup/hold 10.0/0.0 10.0/ 0.0 10.0/0.0 16.0/0.0 ns, min t smckcso cso_b clock to out (330 ? pull-up resistor required) 6667ns, max t smco cclk to data out in readback at 2.5v 6 6 6 7 ns, max cclk to data out in readback at 1.8v 6 6 6 7 ns, max t smckby cclk to busy out in readback at 2.5v 6 6 6 7 ns, max cclk to busy out in readback at 1.8v 6 6 6 7 ns, max f smcck maximum frequency with respect to nominal cclk 100 100 100 70 mhz, max f rbcck maximum readback frequency with respect to nominal cclk 100 100 100 60 mhz, max f mccktol frequency tolerance, master mode with respect to nominal cclk 55 55 55 60 % boundary-scan port timing specifications t taptck /t tcktap tms and tdi setup time before tck/ hold time after tck 3.0/2.0 3.0/2.0 3.0/2.0 4.0/2.0 ns, min t tcktdo tck falling edge to tdo output valid at 2.5v 6667ns, max tck falling edge to tdo output valid at 1.8v 6667ns, max f tck maximum configuration tck clock frequency 66 66 66 33 mhz, max f tckb_min minimum boundary-scan tck clock frequency when usin g ieee std 1149.6 (ac-jtag). minimum operating temperature for ieee std 1149.6 is 0c. 15 15 15 15 mhz, min f tckb maximum boundary-scan tck clock frequency 66 66 66 33 mhz, max ta bl e 5 8 : configuration switching characteristics (cont?d) symbol description speed grade units -3 -2 -1 -1l
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 46 bpi master flash mode programming switching t bpicco (2) addr[25:0], rs[1:0], fcs_b, foe_b, fwe_b outputs valid after cclk rising edge at 2.5v 6667 ns addr[25:0], rs[1:0], fcs_b, foe_b, fwe_b outputs valid after cclk rising edge at 1.8v 6667 ns t bpidcc /t bpiccd setup/hold on d[15:0] data input pins 4.0/0.0 4.0/0.0 4.0/0.0 5.0/0.0 ns t initaddr minimum period of initial addr[25:0] address cycles 3333cclk cycles spi master flash mode programming switching t spidcc /t spidccd din setup/hold before/after the rising cclk edge 3.0/0.0 3.0/0.0 3.0/0.0 3.5/0.0 ns t spiccm mosi clock to out at 2.5v 6 6 6 7 ns mosi clock to out at 1.8v 6 6 6 7 ns t spiccfc fcs_b clock to out at 2.5v 6 6 6 7 ns fcs_b clock to out at 1.8v 6 6 6 7 ns t fsinit /t fsinith fs[2:0] to init_b rising edge setup and hold 2222 s cclk output (master modes) t mcckl master cclk clock low time duty cycle 45/55 45/55 45/55 40/60 %, min/max t mcckh master cclk clock high time duty cycle 45/55 45/55 45/55 40/60 %, min/max cclk input (slave modes) t scckl slave cclk clock minimum low time 2.5 2.5 2.5 2.5 ns, min t scckh slave cclk clock minimum high time 2.5 2.5 2.5 2.5 ns, min dynamic reconfiguration port (drp) for mmcm before and after dclk f dck maximum frequency for dclk 200 200 200 200 mhz t mmcmdck_daddr / t mmcmckd_daddr daddr setup/hold 1.25/ 0.00 1.40/ 0.00 1.63/ 0.00 1.64/ 0.00 ns t mmcmdck_di /t mmcmckd_di di setup/hold 1.25/ 0.00 1.40/ 0.00 1.63/ 0.00 1.64/ 0.00 ns t mmcmdck_den /t mmcmckd_den den setup/hold time 1.25/ 0.00 1.40/ 0.00 1.63/ 0.00 1.64/ 0.00 ns t mmcmdck_dwe /t mmcmckd_dwe dwe setup/hold time 1.25/ 0.00 1.40/ 0.00 1.63/ 0.00 1.64/ 0.00 ns t mmcmcko_do clk to out of do (3) 2.60 3.02 3.64 3.68 ns t mmcmcko_drdy clk to out of drdy 0.32 0.34 0.38 0.38 ns notes: 1. to support longer delays in configuration, use the design solutions described in virtex-6 fpga configuration user guide . 2. only during configuration, the last edge is determined by a weak pull-up/pull-down resistor in the i/o. 3. do will hold until next drp operation. ta bl e 5 8 : configuration switching characteristics (cont?d) symbol description speed grade units -3 -2 -1 -1l
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 47 clock buffers and networks ta bl e 5 9 : global clock switching characte ristics (incl uding bufgctrl) symbol description speed grade units -3 -2 -1 -1l t bccck_ce /t bcckc_ce (1) ce pins setup/hold 0.11/ 0.00 0.13/ 0.00 0.16/ 0.00 0.13/ 0.00 ns t bccck_s /t bcckc_s (1) s pins setup/hold 0.11/ 0.00 0.13/ 0.00 0.16/ 0.00 0.13/ 0.00 ns t bccko_o (2) bufgctrl delay from i0/i1 to o 0.07 0.08 0.10 0.10 ns maximum frequency f max global clock tree (bufg) 800 750 700 667 mhz notes: 1. t bccck_ce and t bcckc_ce must be satisfied to assure glitch-free operation of the global clock when switching between clocks. these parameters do not apply to the bufgmux_virtex4 primitive that assures glitch-free operation. the other global clock setup and h old times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when swit ching between clocks. 2. t bgcko_o (bufg delay from i0 to o) values are the same as t bccko_o values. ta bl e 6 0 : input/output clock switching characteristics (bufio) symbol description speed grade units -3 -2 -1 -1l t biocko_o clock to out delay from i to o 0.14 0.16 0.18 0.21 ns maximum frequency f max i/o clock tree (bufio) 800 800 710 710 mhz ta bl e 6 1 : regional clock switching characteristics (bufr) symbol description speed grade units -3 -2 -1 -1l t brcko_o clock to out delay from i to o 0.56 0.62 0.73 0.82 ns t brcko_o_byp clock to out delay from i to o with divide bypass attribute set 0.28 0.31 0.36 0.41 ns t brdo_o propagation delay from clr to o 0.69 0.74 0.80 1.12 ns maximum frequency f max (1) regional clock tree (bufr) 500 420 300 300 mhz notes: 1. the maximum input frequency to the bufr is the bufio f max frequency. ta bl e 6 2 : horizontal clock buffer switching characteristics (bufh) symbol description speed grade units -3 -2 -1 -1l t bhcko_o bufh delay from i to o 0.10 0.11 0.13 0.15 ns t bhcck_ce /t bhckc_ce ce pin setup and hold 0.04/ 0.04 0.04/ 0.04 0.05/ 0.05 0.04/ 0.04 ns maximum frequency f max horizontal clock buffer (bufh) 800 750 700 667 mhz
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 48 mmcm switching characteristics ta bl e 6 3 : mmcm specification symbol description speed grade units -3 -2 -1 -1l f inmax maximum input clock frequency (1) 800 750 700 700 mhz f inmin minimum input clock frequency 10 10 10 10 mhz f injitter maximum input clock period jitter < 20% of clock input period or 1 ns max f induty allowable input duty cycle: 19?49 mhz 25/75 % allowable input duty cycle: 50?199 mhz 30/70 % allowable input duty cycle: 200?399 mhz 35/65 % allowable input duty cycle: 400?499 mhz 40/60 % allowable input duty cycle: >500 mhz 45/55 % f min_psclk minimum dynamic phase shift clock frequency 0.01 0.01 0.01 0.01 mhz f max_psclk maximum dynamic phase shift clock frequency 550 500 450 450 mhz f vcomin minimum mmcm vco frequency 600 600 600 600 mhz f vcomax maximum mmcm vco frequency 1600 1440 1200 1200 mhz f bandwidth low mmcm bandwidth at typical (2) 1.00 1.00 1.00 1.00 mhz high mmcm bandwidth at typical (2) 4.00 4.00 4.00 4.00 mhz t statphaoffset static phase offset of the mmcm outputs (3) 0.12 0.12 0.12 0.12 ns t outjitter mmcm output jitter (4) note 1 t outduty mmcm output clock duty cycle precision (5) 0.15 0.20 0.20 0.20 ns t lockmax mmcm maximum lock time 100 100 100 100 s f outmax mmcm maximum output frequency 800 750 700 700 mhz f outmin mmcm minimum output frequency (6)(7) 4.69 4.69 4.69 4.69 mhz t extfdvar external clock feedback variation < 20% of clock input period or 1 ns max rst minpulse minimum reset pulse width 1.5 1.5 1.5 1.5 ns f pfdmax maximum frequency at the phase frequency detector with bandwidth set to high or optimized (8) 550 500 450 450 mhz maximum frequency at the phase frequency detector with bandwidth set to low 300 300 300 300 mhz f pfdmin minimum frequency at the phase frequency detector with bandwidth set to high or optimized 135 135 135 135 mhz minimum frequency at the phase frequency detector with bandwidth set to low 10 10 10 10 mhz t fbdelay maximum delay in the feedback path 3 ns max or one clkin cycle t mmcmdck_psen / t mmcmckd_psen setup and hold of phase shift enable 1.04 0.00 1.04 0.00 1.04 0.00 1.04 0.00 ns t mmcmdck_psincdec / t mmcmckd_psincdec setup and hold of phase shift increment/decrement 1.04 0.00 1.04 0.00 1.04 0.00 1.04 0.00 ns
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 49 virtex-6 device pin-to-pin output parameter guidelines all devices are 100% functionally tested. the representative values for typical pin locations and normal clock loading are listed in ta bl e 6 4 . values are expressed in nanoseconds unless otherwise noted. t mmcmcko_psdone phase shift clock-to-out of psdone 0.32 0.34 0.38 0.38 ns notes: 1. when divclk_divide = 3 or 4, f inmax is 315 mhz. 2. the mmcm does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequen cies. 3. the static offset is measured between any mmcm outputs with identical phase. 4. values for this parameter are available in the architecture wizard. 5. includes global clock buffer. 6. calculated as f vco /128 assuming output duty cycle is 50%. 7. when cascade4_out = true, f outmin is 0.036 mhz. 8. in ise software 12.3 (or earlier versions supporting the virtex-6 family), the phase frequency detector optimized bandwidth s etting is equivalent to the high bandwidth setting. starting with ise software 12.4, the optimized bandwidth setting is automatically adj usted to low when the software can determine that the phase frequency detector input is less than 135 mhz. ta bl e 6 4 : global clock input to output delay without mmcm symbol description device speed grade units -3 -2 -1 -1l lvcmos25 global clock input to output delay us ing output flip-flop, 12ma, fast slew rate, without mmcm. t ickof global clock input and outff without mmcm xc6vlx75t 4.91 5.32 5.88 6.02 ns xc6vlx130t 4.89 5.33 6.00 6.13 ns xc6vlx195t 5.02 5.46 6.13 6.27 ns xc6vlx240t 5.02 5.46 6.13 6.27 ns xc6vlx365t 5.30 5.75 6.43 6.37 ns xc6vlx550t n/a 6.02 6.72 6.60 ns xc6vlx760 n/a 6.26 6.97 6.87 ns xc6vsx315t 5.40 5.85 6.54 6.49 ns xc6vsx475t n/a 6.01 6.71 6.61 ns xc6vhx250t 5.18 5.63 6.30 n/a ns xc6vhx255t 5.20 5.66 6.34 n/a ns xc6vhx380t 5.38 5.84 6.53 n/a ns xc6vhx565t n/a 5.85 6.56 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. ta bl e 6 3 : mmcm specification (cont?d) symbol description speed grade units -3 -2 -1 -1l
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 50 ta bl e 6 5 : global clock input to output delay with mmcm symbol description device speed grade units -3 -2 -1 -1l lvcmos25 global clock input to output delay us ing output flip-flop, 12ma, fast slew rate, with mmcm. t ickofmmcmgc global clock input and outff with mmcm xc6vlx75t 2.34 2.50 2.77 2.85 ns xc6vlx130t 2.35 2.51 2.78 2.87 ns xc6vlx195t 2.36 2.52 2.79 2.88 ns xc6vlx240t 2.36 2.52 2.79 2.88 ns xc6vlx365t 2.37 2.53 2.79 2.89 ns xc6vlx550t n/a 2.55 2.82 2.93 ns xc6vlx760 n/a 2.54 2.82 2.92 ns xc6vsx315t 2.35 2.51 2.79 2.87 ns xc6vsx475t n/a 2.43 2.70 2.79 ns xc6vhx250t 2.36 2.53 2.80 n/a ns xc6vhx255t 2.46 2.63 2.91 n/a ns xc6vhx380t 2.39 2.59 2.83 n/a ns xc6vhx565t n/a 2.54 2.81 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. mmcm output jitter is already included in the timing calculation. ta bl e 6 6 : clock-capable clock input to output delay with mmcm symbol description device speed grade units -3 -2 -1 -1l lvcmos25 clock-capable clock input to output dela y using output flip-flop, 12ma, fast slew rate, with mmcm. t ickofmmcmcc clock-capable clock input and outff with mmcm xc6vlx75t 2.22 2.38 2.63 2.72 ns xc6vlx130t 2.24 2.39 2.65 2.74 ns xc6vlx195t 2.24 2.40 2.65 2.75 ns xc6vlx240t 2.24 2.40 2.65 2.75 ns xc6vlx365t 2.25 2.42 2.65 2.76 ns xc6vlx550t n/a 2.43 2.68 2.80 ns xc6vlx760 n/a 2.42 2.69 2.79 ns xc6vsx315t 2.23 2.38 2.65 2.73 ns xc6vsx475t n/a 2.30 2.57 2.66 ns xc6vhx250t 2.25 2.41 2.67 n/a ns xc6vhx255t 2.35 2.51 2.78 n/a ns xc6vhx380t 2.27 2.43 2.69 n/a ns xc6vhx565t n/a 2.41 2.68 n/a ns notes: 1. listed above are representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible iob and clb flip-flops are clocked by the global clock net. 2. mmcm output jitter is already included in the timing calculation.
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 51 virtex-6 device pin-to-pin input parameter guidelines all devices are 100% functionally tested. the representative values for typical pin locations and normal clock loading are listed in ta bl e 6 7 . values are expressed in nanoseconds unless otherwise noted. ta bl e 6 7 : global clock input setup and hold without mmcm symbol description device speed grade units -3 -2 -1 -1l input setup and hold time relative to global clock input signal for lvcmos25 standard. (1) t psfd / t phfd full delay (legacy delay or default delay) global clock input and iff (2) without mmcm xc6vlx75t 1.33/ 0.03 1.44/ 0.03 1.75/ 0.03 2.18/ ?0.22 ns xc6vlx130t 1.31/ ?0.08 1.54/ ?0.08 1.88/ ?0.08 2.31/ ?0.12 ns xc6vlx195t 1.36/ ?0.11 1.60/ ?0.11 1.97/ ?0.11 2.40/ ?0.25 ns xc6vlx240t 1.36/ ?0.11 1.60/ ?0.11 1.97/ ?0.11 2.40/ ?0.25 ns xc6vlx365t 1.79/ ?0.28 1.87/ ?0.28 2.17/ ?0.28 2.48/ ?0.24 ns xc6vlx550t n/a 2.22/ ?0.12 2.36/ ?0.12 2.77/ ?0.26 ns xc6vlx760 n/a 2.19/ ?0.24 2.35/ ?0.24 2.71/ ?0.21 ns xc6vsx315t 1.75/ ?0.09 1.85/ ?0.09 2.06/ ?0.09 2.47/ ?0.24 ns xc6vsx475t n/a 2.14/ ?0.14 2.31/ ?0.14 2.71/ ?0.30 ns xc6vhx250t 1.93/ ?0.22 2.04/ ?0.22 2.25/ ?0.22 n/a ns xc6vhx255t 1.81/ ?0.33 2.11/ ?0.33 2.56/ ?0.33 n/a ns xc6vhx380t 1.93/ ?0.11 2.04/ ?0.11 2.25/ ?0.11 n/a ns xc6vhx565t n/a 2.38/ ?0.12 2.54/ ?0.12 n/a ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch 3. a zero "0" hold time listing indicates no hold time or a negative hold time. negative values can not be guaranteed "best-case ", but if a "0" is listed, there is no positive hold time.
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 52 ta bl e 6 8 : global clock input setup and hold with mmcm symbol description device speed grade units -3 -2 -1 -1l input setup and hold time relative to global clock input signal for lvcmos25 standard. (1) t psmmcmgc / t phmmcmgc no delay global clock input and iff (2) with mmcm xc6vlx75t 1.45/ ?0.18 1.57/ ?0.18 1.72/ ?0.18 1.78/ ?0.08 ns xc6vlx130t 1.53/ ?0.18 1.65/ ?0.18 1.81/ ?0.18 1.87/ ?0.07 ns xc6vlx195t 1.54/ ?0.17 1.66/ ?0.17 1.82/ ?0.17 1.87/ ?0.08 ns xc6vlx240t 1.54/ ?0.17 1.66/ ?0.17 1.82/ ?0.17 1.87/ ?0.08 ns xc6vlx365t 1.55/ ?0.18 1.67/ ?0.18 1.83/ ?0.18 1.87/ ?0.07 ns xc6vlx550t n/a 1.84/ ?0.17 2.02/ ?0.17 2.06/ ?0.06 ns xc6vlx760 n/a 2.26/ ?0.13 2.49/ ?0.13 2.06/ ?0.03 ns xc6vsx315t 1.56/ ?0.18 1.68/ ?0.18 1.84/ ?0.18 1.89/ ?0.08 ns xc6vsx475t n/a 1.85/ ?0.23 2.03/ ?0.23 2.07/ ?0.13 ns xc6vhx250t 1.52/ ?0.17 1.64/ ?0.17 1.80/ ?0.17 n/a ns xc6vhx255t 1.52/ ?0.12 1.64/ ?0.12 1.80/ ?0.12 n/a ns xc6vhx380t 1.68/ ?0.16 1.81/ ?0.16 1.99/ ?0.16 n/a ns xc6vhx565t n/a 1.81/ ?0.16 1.99/ ?0.16 n/a ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle distortion incurred using various standards.
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 53 ta bl e 6 9 : clock-capable clock input setup and hold with mmcm symbol description device speed grade units -3 -2 -1 -1l input setup and hold time relative to clock-ca pable clock input signal for lvcmos25 standard. (1) t psmmcmcc / t phmmcmcc no delay clock-capable clock input and iff (2) with mmcm xc6vlx75t 1.56/ ?0.25 1.69/ ?0.25 1.86/ ?0.25 1.91/ ?0.15 ns xc6vlx130t 1.64/ ?0.25 1.78/ ?0.25 1.95/ ?0.25 2.00/ ?0.14 ns xc6vlx195t 1.65/ ?0.24 1.79/ ?0.24 1.96/ ?0.24 2.01/ ?0.15 ns xc6vlx240t 1.65/ ?0.24 1.79/ ?0.24 1.96/ ?0.24 2.01/ ?0.15 ns xc6vlx365t 1.66/ ?0.25 1.79/ ?0.25 1.97/ ?0.25 2.02/ ?0.15 ns xc6vlx550t n/a 1.97/ ?0.24 2.16/ ?0.24 2.19/ ?0.14 ns xc6vlx760 n/a 2.39/ ?0.20 2.63/ ?0.20 2.21/ ?0.10 ns xc6vsx315t 1.67/ ?0.25 1.80/ ?0.25 1.98/ ?0.25 2.03/ ?0.16 ns xc6vsx475t n/a 1.98/ ?0.29 2.17/ ?0.29 2.21/ ?0.20 ns xc6vhx250t 1.63/ ?0.24 1.76/ ?0.24 1.94/ ?0.24 n/a ns xc6vhx255t 1.63/ ?0.19 1.76/ ?0.19 1.94/ ?0.19 n/a ns xc6vhx380t 1.80/ ?0.23 1.94/ ?0.23 2.13/ ?0.23 n/a ns xc6vhx565t n/a 1.94/ ?0.23 2.13/ ?0.23 n/a ns notes: 1. setup and hold times are measured over worst case conditions (process, voltage, temperature). setup time is measured relative to the global clock input signal using the slowest process, highest temperature, and lowest voltage. hold time is measured relative to the global clock input signal using the fastest process, lowest temperature, and highest voltage. 2. iff = input flip-flop or latch 3. use ibis to determine any duty-cycle distortion incurred using various standards.
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 54 clock switching characteristics the parameters in this section provide the necessary valu es for calculating timing budgets for virtex-6 fpga clock transmitter and receiver data-valid windows. ta bl e 7 0 : duty cycle distortion and clock-tree skew symbol description device speed grade units -3 -2 -1 -1l t dcd_clk global clock tree duty cycle distortion (1) all 0.12 0.12 0.12 0.12 ns t ckskew global clock tree skew (2) xc6vlx75t 0.15 0.16 0.18 0.17 ns xc6vlx130t 0.25 0.26 0.29 0.28 ns xc6vlx195t 0.26 0.27 0.31 0.30 ns xc6vlx240t 0.26 0.27 0.31 0.30 ns xc6vlx365t 0.28 0.29 0.31 0.31 ns xc6vlx550t n/a 0.50 0.54 0.54 ns xc6vlx760 n/a 0.51 0.56 0.56 ns xc6vsx315t 0.27 0.28 0.32 0.30 ns xc6vsx475t n/a 0.39 0.44 0.42 ns xc6vhx250t 0.25 0.26 0.29 n/a ns xc6vhx255t 0.35 0.37 0.41 n/a ns xc6vhx380t 0.45 0.47 0.52 n/a ns xc6vhx565t n/a 0.46 0.51 n/a ns t dcd_bufio i/o clock tree duty cycle distortion all 0.08 0.08 0.08 0.08 ns t bufioskew i/o clock tree skew across one clock region all 0.03 0.03 0.03 0.02 ns t bufioskew2 i/o clock tree skew across three clock regions all 0.10 0.12 0.23 0.12 ns t dcd_bufr regional clock tree duty cycle distortion all 0.15 0.15 0.15 0.15 ns notes: 1. these parameters represent the worst-case duty cycle distortion observable at the pins of the device using lvds output buffer s. for cases where other i/o standards are used, ibis can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times. 2. the t ckskew value represents the worst-case clock-tree skew observable between sequential i/o elements. significantly less clock-tree skew exists for i/o registers that are close to each other and fed by the same or adjacent clock-tree branches. use the xilinx fpga_editor and timing analyzer tools to evaluate clock skew specific to your application.
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 55 ta bl e 7 1 : package skew symbol description device package value units t pkgskew package skew (1) xc6vlx75t ff484 82 ps ff784 108 ps xc6vlx130t ff484 78 ps ff784 126 ps ff1156 165 ps xc6vlx195t ff784 128 ps ff1156 131 ps xc6vlx240t ff784 146 ps ff1156 182 ps ff1759 187 ps xc6vlx365t ff1156 137 ps ff1759 156 ps xc6vlx550t ff1759 159 ps ff1760 202 ps xc6vlx760 ff1760 194 ps xc6vsx315t ff1156 139 ps ff1759 162 ps xc6vsx475t ff1156 131 ps ff1759 161 ps xc6vhx250t ff1154 159 ps xc6vhx255t ff1155 ps ff1923 220 ps xc6vhx380t ff1154 ps ff1155 172 ps ff1923 227 ps ff1924 220 ps xc6vhx565t ff1923 ps ff1924 ps notes: 1. these values represent the worst-case skew between any two selectio resources in the package: shortest flight time to longest flight time from pad to ball (7.0 ps per mm). 2. package trace length information is available for these device/package combinations. this information can be used to deskew t he package.
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 56 revision history the following table shows the revision history for this document: ta bl e 7 2 : sample window symbol description device speed grade units -3 -2 -1 -1l t samp sampling error at receiver pins (1) all 510 560 610 670 ps t samp_bufio sampling error at receiver pins using bufio (2) all 300 350 400 440 ps notes: 1. this parameter indicates the total sampling error of virtex-6 fpga ddr input registers, measured across voltage, temperature, and process. the characterization methodology uses the mmcm to capture the ddr input registers? edges of operation. these measureme nts include: - clk0 mmcm jitter - mmcm accuracy (phase offset) - mmcm phase shift resolution these measurements do not include package or clock tree skew. 2. this parameter indicates the total sampling error of virtex-6 fpga ddr input registers, measured across voltage, temperature, and process. the characterization methodology uses the bufio clock network and iodelay to capture the ddr input registers? edges of operation. these measurements do not include package or clock tree skew. ta bl e 7 3 : pin-to-pin setup/hold and clock-to-out symbol description speed grade units -3 -2 -1 -1l data input setup and hold times relative to a forwarded clock input pin using bufio t pscs /t phcs setup/hold of i/o clock ?0.28 1.09 ?0.28 1.16 ?0.28 1.33 ?0.18 1.79 ns pin-to-pin clock-to -out using bufio t ickofcs clock-to-out of i/o clock 4.22 4.59 5.22 5.63 ns date version description of revisions 06/24/09 1.0 initial xilinx release. 07/16/09 1.1 revised the maximum v ccaux and v in numbers in table2, page2 . removed empty column from table 3, page 3 . revised specifications on table 20, page 12 . updated table 38, page 21 and added notes 1 and 2. revised t dlycco_rdy , t idelayctrl_rpw , and t idelaypat_jit in table 52, page 36 . updated table 57, page 41 to more closely match the dsp48e1 speed specifications. updated t taptck /t tcktap in table 58, page 44 . updated xc6vlx130t parameters in ta b l e 6 7 through table 69, page 53 . 08/19/09 1.2 added values for -1l voltages and speed grade in all pertinent tables. added v fs and notes to ta bl e 1 and ta b l e 2 . removed dv ppin from the example in figure 2 . added networking applications to table 41, page 24 . changed and added to the block ram f max section in table 56, page 40 including removing note 12. changed f pfdmax values and corrected units for t statphaoffset and t outduty in table 63, page 48 . updated table 70, page 54 . 09/16/09 2.0 added virtex-6 hxt devices to entire document including gth transceiver specifications . updated speed specifications as described in switching characteristics , includes changes in ta b l e 5 0 , ta b l e 5 6 , ta bl e 5 7 , and ta b l e 6 5 through ta bl e 6 9 . comprehensive changes to ta bl e 1 4 , ta b l e 1 5 , and ta b l e 1 6 . added conditions to d vppout and revised description of t oskew in ta b l e 1 7 . removed v ise specification and note from ta b l e 1 8 . added note 3 to ta b l e 2 3 . updated note 3 in ta b l e 2 4 . updated lvcmos25 delays in ta b l e 4 4 . updated specification for t iotphz in ta bl e 4 5 . removed t bufhskew from table 70, page 54 and added values for t bufioskew . added values in ta b l e 7 3 .
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 57 01/18/10 2.1 changed absolute maximum ratings for both v in and v ts in ta bl e 1 . added data to ta bl e 3 . added data to ta b l e 5 . updated sstl15 in ta bl e 7 . updated v ocm and v od values in ta b l e 8 . added efuse endurance ta b l e 1 2 . added values to v mgtrefclk and v in in table 13, page 10 . added values and updated tables in the gtx transceiver specifications and gth transceiver specifications sections. added ta b l e 2 7 and figure 4 . revised parameters and values in ta b l e 3 9 . updated table 40, page 22 . added data to ta bl e 4 1 . updated speed specification to v1.04 with appropriate changes to ta b l e 4 2 and ta b l e 4 3 including production release of the xc6vlx240t for -1 and -2 speed grades. speed specification changes and numerous updates also made to ta bl e 4 4 , and ta b l e 4 8 through ta b l e 7 0 . added data to ta bl e 7 2 and ta b l e 7 3 . 02/09/10 2.2 revised description of c in in ta b l e 3 . clarified values in ta b l e 5 . fixed sdr lvds unit error in ta b l e 4 1 . 04/12/10 2.3 added note 3 and update value of n in ta b l e 3 . clarified simultaneous power-down in power-on power supply requirements . updated external reference junction temperatures in ta bl e 4 0 , analog-to-digital specifications . updated speed specification to v1 .05 with appropriate changes to ta bl e 4 2 and ta b l e 4 3 including production release of the xc6vlx130t for -1 and -2 speed grades. fixed note 4 in ta b l e 4 7 . increased the -2 specification for f idelayctrl_ref and clarified units for t idelaypat_jit in ta b l e 5 2 . added note 1 to ta b l e 6 1 . 05/11/10 2.4 updated f rxrec in ta b l e 2 2 . revised f idelayctrl_ref in ta b l e 5 2 . removed t rcko_parity_ecc : clock clk to eccparity in standard ecc mode row in ta bl e 5 6 . added xc6vlx130t values to ta b l e 7 1 . 05/26/10 2.5 added xc6vlx195t data to ta b l e 5 . updated values in ta b l e 2 2 including adding note 2 and note 3. updated speed specification to v1 .06 with appropriate changes to ta b l e 4 2 and ta bl e 4 3 including production release of the xc6vlx195t for -1 and -2 speed grades. added xc6vlx195t values to ta b l e 7 1 . 07/16/10 2.6 changed ta b l e 4 2 and ta b l e 4 3 to production status on the -3 speed grade xc6vlx130t, xc6vlx195t, and xc6vlx240t devices. added xc6vhx250tdata to ta b l e 4 and ta bl e 7 1 . added note 6 to ta b l e 6 3 . 07/23/10 2.7 changed ta bl e 4 2 and ta bl e 4 3 to production status on the xc6vlx75t, xc6vlx365t, xc6vlx550t, xc6vlx760, xc6vsx315t, and xc6vsx475t devices using ise 12.2 software with speed specification v1.08. updated v cmoutdc equation to mgtavtt ? d vppout /4 in ta b l e 1 7 . updated some -3, -2, -1 specifications in ta b l e 6 4 through ta b l e 7 1 . added and updated -1l specifications to ta b l e 4 1 and for most switching characteristics tables. 07/30/10 2.8 changed ta b l e 4 2 and ta b l e 4 3 to production status on the -1l speed grade for the xc6vlx130t, xc6vlx195t, xc6vlx240t, xc6vlx365t, and xc6vlx 550t devices using ise 12.2 software with current speed specifications. also updated the sp eed specifications for xc6vlx75t, xc6vlx550t, and xc6vsx315t. updated v ccint specifications for -1l speed gra de industrial temperature range devices in ta bl e 2 . 09/20/10 2.9 in ta b l e 3 2 , changed f gpllmax specification in -3 column from 5.951 to 5.591. in ta bl e 4 0 , changed f max for the dclk from 250 mhz to 80 mhz. 10/18/10 2.10 the specification change in version 2.9, ta b l e 4 0 is described in xcn10032 , virtex-6 fpga: gtx transceiver user guide, family data sh eet (sysmon dclk), an d jtag id changes in this version (2.10), -1l(i) data is added to ta b l e 4 and clarified in note 2. changed ta b l e 4 2 and ta b l e 4 3 to production status on the -1l speed gr ade xc6vlx75t, xc6vlx760, xc6vsx315t, and xc6vsx475t devices using ise 12.3 software with current speed specifications. revised the xc6vlx760 -1l speed specification for t phmmcmgc in ta b l e 6 8 and t phmmcmcc in ta bl e 6 9 . 01/17/11 2.11 changed in ta b l e 4 2 and ta b l e 4 3 to production status on the xc6vhx250t devices using ise 12.4 software with current speed specifications. added industrial temperature range (t j ) recommended specifications to ta b l e 2 ; including specific ranges for the -2i xc6vsx475t, xc6vlx550t, xc6vlx760, and xc6vhx565tdevices. added note 3 to ta bl e 3 6 and maximum total jitter values. added note 4 to ta bl e 3 7 and maximum sinusoidal jitter values. added note 2 to ta bl e 4 3 . revised f max descriptions in ta bl e 5 6 and added note 12. added note 8 to f pfdmin in ta b l e 6 3 . the following revisions are due to specification changes as described in xcn11009 , virtex-6 fpga: data sheet, user guides, and jtag id updates . in ta b l e 5 8 : configuration switching characteristics , page 44 , revised -1l specifications for t por , f mcck , f mccktol , t smcscck , t smcckw , f rbcck , f tck , f tckb , t mcckl , and t mcckh . in ta bl e 6 3 : mmcm specification , added bandwidth settings to f pfdmin and added note 1. date version description of revisions
virtex-6 fpga data sheet: dc and switching characteristics ds152 (v2.11) january 17, 2011 www.xilinx.com advance product specification 58 notice of disclaimer the xilinx hardware fpga and cpld devices referred to herein (?products?) are subject to the terms and conditions of the xilinx limite d warranty which can be viewed at http://www.xilinx.com/warranty.htm . this limited warranty does not extend to any use of products in an application or environment that is not within the specifications stated in the xilinx data sheet. all specifications are subject to change without notice. products are not designed or intended to be fail-safe or for use in any application requiring fail-safe performance, such as life-support or safety devic es or systems, or any other application that invokes the potential risks of death, personal injury, or property or environmental damage (?critical applications?). use of products in critical applications is at the sole risk of customer, subject to applicable laws and regulations.

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